K7A403609B
K7A403209B
K7A401809B
Document Title
128Kx36/x32 & 256Kx18 Synchronous SRAM
128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Pipelined Burst SRAM
Revision History
Rev. No
0.0
0.1
History
1. Initial draft
1. Changed DC parameters
Icc ; from 570mA to 490mA at -30,
from 520mA to 440mA at -27,
from 470mA to 400mA at -25,
from 440mA to 360mA at -22,
from 400mA to 330mA at -20,
from 370mA to 310mA at -18,
I
SB
; from 200mA
from 190mA
from 180mA
from 170mA
from 160mA
from 150mA
to
to
to
to
to
to
180mA at -30,
170mA at -27,
160mA at -25,
155mA at -22,
150mA at -20,
140mA at -18,
Draft Date
May. 15. 2001
June. 12. 2001
Remark
Preliminary
Preliminary
I
SB1
; from 100mA to 80mA
2. Input set-up(tAS,tSS,tDS,tWS,tADVS,tCSS) from 0.6ns to 0.7ns at -30
0.2
0.3
1. Delete Pass-Through
1. Changed Input set-up(tAS,tSS,tDS,tWS,tADVS,tCSS)
- from 0.8ns to 1.0ns at -25
- from 075ns to 0.8ns at -27
- from 0.7ns to 0.8ns at -30
1. Add x32 org and industrial range temperature
1. Final spec release
2. Changed Pin Capacitance
- Cin ; from 5pF to 4pF
- Cout ; from 7pF to 6pF
June. 25. 2001
July. 31. 2001
Preliminary
Preliminary
0.4
1.0
Aug. 11. 2001
Nov. 15. 2001
Preliminary
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Nov 2001
Rev 1.0
K7A403609B
K7A403209B
K7A401809B
128Kx36/x32 & 256Kx18 Synchronous SRAM
128Kx36 & 128Kx32 & 256Kx18-Bit Synchronous Pipelined Burst SRAM
FEATURES
• Synchronous Operation.
• 2 Stage Pipelined operation with 4 Burst.
• On-Chip Address Counter.
• Self-Timed Write Cycle.
• On-Chip Address and Control Registers.
• V
DD
= 3.3V+0.3V/-0.165V Power Supply.
• V
DDQ
Supply Voltage 3.3V+0.3V/-0.165V for 3.3V I/O
or 2.5V+0.4V/-0.125V for 2.5V I/O.
• 5V Tolerant Inputs Except I/O Pins.
• Byte Writable Function.
• Global Write Enable Controls a full bus-width write.
• Power Down State via ZZ Signal.
• LBO Pin allows a choice of either a interleaved burst or a linear
burst.
• Three Chip Enables for simple depth expansion with No Data Cont-
nention ; 2cycle Enable, 1cycle Disable.
• Asynchronous Output Enable Control.
• ADSP, ADSC, ADV Burst Control Pins.
• TTL-Level Three-State Output.
• 100-TQFP-1420A .
• Operating in commeical and industrial temperature range.
GENERAL DESCRIPTION
The K7A403609B, K7A403209B and K7A401809B are
4,718,592-bit Synchronous Static Random Access Memory
designed for high performance second level cache of Pen-
tium and Power PC based System.
It is organized as 128K(256K) words of 36(18) bits and inte-
grates address and control registers, a 2-bit burst address
counter and added some new functions for high perfor-
mance cache RAM applications; GW, BW, LBO, ZZ. Write
cycles are internally self-timed and synchronous.
Full bus-width write is done by GW, and each byte write is
performed by the combination of WEx and BW when GW is
high. And with CS
1
high, ADSP is blocked to control signals.
Burst cycle can be initiated with either the address status
processor(ADSP) or address status cache controller(ADSC)
inputs. Subsequent burst addresses are generated inter-
nally in the system′s burst sequence and are controlled by
the burst address advance(ADV) input.
LBO pin is DC operated and determines burst sequence(lin-
ear or interleaved).
ZZ pin controls Power Down State and reduces Stand-by
current regardless of CLK.
The K7A403609B, K7A403209B and K7A401809B are fab-
ricated using SAMSUNG′s high performance CMOS tech-
nology and is available in a 100pin TQFP package. Multiple
power and ground pins are utilized to minimize ground
bounce.
FAST ACCESS TIMES
PARAMETER
Cycle Time
Clock Access Time
Output Enable Access Time
Symbol
tCYC
tCD
tOE
-30 -27 -25
3.3 3.6
2.2 2.2
2.2 2.2
4.0
2.4
2.4
-22 -20 Unit
4.4
2.6
2.6
5.0
2.8
2.8
ns
ns
ns
LOGIC BLOCK DIAGRAM
CLK
LBO
CONTROL
REGISTER
ADV
ADSC
BURST CONTROL
LOGIC
BURST
ADDRESS
A′0~A′1
COUNTER
A0~A1
128Kx36/32 , 256Kx18
MEMORY
ARRAY
ADSP
A0~A16
or A0~A17
ADDRESS
REGISTER
A2~A16
or A2~A17
CS1
CS2
CS2
GW
BW
WEx
(x=a,b,c,d or a,b)
OE
ZZ
DQa0 ~ DQd7
DQPa ~ DQPd
DATA-IN
REGISTER
CONTROL
REGISTER
or DQa0 ~ DQb7
DQPa ~ DQPb
CONTROL
LOGIC
OUTPUT
REGISTER
BUFFER
36/32 or 18
-3-
Nov 2001
Rev 1.0
Microcontroller MCU
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