KAA00B606A
Document Title
Multi-Chip Package MEMORY
Preliminary
MCP MEMORY
256M Bit(16Mx16) Nand Flash/64M Bit(4Mx16) UtRAM/128M Bit(2Mx16x4Banks) MobileSDRAM
Revision History
Revision No. History
0.0
0.1
Initial issue.
<UtRAM>
Revised
- Changed I
CC
2u(Max.) from 35mA to 40mA
- Changed I
CC
2u(Typ.) from 30mA to 35mA
- Changed I
SBD
(Max.) from 10µA to 20µA
<UtRAM>
Errata Correction
-Changed UtRAM Speed from 90/100ns to 85ns
<Mobile SDRAM>
-Addtion of Timing Diagram
<Mobile SDRAM>
- Errata Correction
Changed Unit of t
ARFC
/ t
SRFX
from CLK to ns
- Addition of Internal TCSR option
- Removal of External TCSR.
Finalize
Draft Date
July 18, 2002
Remark
Preliminary
November 26. 2002 Preliminary
0.11
January 23. 2003
Preliminary
0.2
February 24. 2003
Preliminary
1.0
May 30. 2003
Final
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s web site.
http://samsungelectronics.com/semiconductors/products/products_index.html
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
-1-
Revision 1.0
May 2003
KAA00B606A
Multi-Chip Package MEMORY
Preliminary
MCP MEMORY
256M Bit (16Mx16) Nand Flash/64M Bit (4Mx16) UtRAM/128M Bit (2Mx16x4Banks) Mobile SDRAM
FEATURES
<Common>
•
Power Supply Voltage
- NAND, SDRAM : 1.7~2.0V
- UtRAM : 2.7~3.1V
•
Data Output Power : 1.7~2.0V
•
Operating Temperature : -25°C ~ 85°C
•
Package : 127-ball TBGA Type - 10.5x12mm, 0.8mm pitch
<NAND>
•
Organization
- Memory Cell Array : (16M + 512K)bit x 16bit
- Data Register : (256 + 8)bit x16bit
•
Automatic Program and Erase
- Page Program : (256 + 8)Word
- Block Erase : (8K + 256)Word
•
Page Read Operation
- Page Size : (256 + 8)Word
- Random Access : 10µs(Max.)
- Serial Page Access : 50ns(Min.)
•
Fast Write Cycle Time
- Program time : 200µs(Typ.)
- Block Erase Time : 2ms(Typ.)
•
Command/Address/Data Multiplexed I/O Port
•
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
•
Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
•
Command Register Operation
•
Intelligent Copy-Back
<UtRAM>
•
Process Technology : CMOS
•
Organization : 4M x 16 bit
•
Read Access Time : 85ns
•
Three State Outputs
•
Compatible with Low Power SRAM
•
Deep Power Down : Memory cell data holds invalid
<SDRAM>
• 1.8V power supply.
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• Frequency : 105MHz, 66MHz
• MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• Special option for Mobile application.
-. PASR(Partial Array Self Refresh) with EMRS cycle.
-. Internal TCSR(Temperature Compensated Self Refresh)
-. DS(Driver Strength Control)
• All inputs are sampled at the positive going edge of the sys-
tem
clock.
• Burst read single-bit write operation.
• Special Function Support.
-. DPD Mode by External pin
• DQM for masking.
• Auto refresh.
• 64ms refresh period (4K cycle).
GENERAL DESCRIPTION
The KAA00B606A is a Multi Chip Package Memory which combines 256Mbit Nand Flash Memory, 64Mbit Unit Transistor CMOS
RAM and 128Mbit synchronous high data rate Dynamic RAM.
256Mbit NAND Flash memory is organized as 16M x16 bits and 64Mbit UtRAM is organized as 4M x16 bits and 128Mbit SDRAM is
organized as 2M x16 bits x4 banks.
In 256Mbit NAND Flash, a 264-word page program can be typically achieved within 200us and an 8K-word block erase can be typi-
cally achieved within 2ms. In serial read operation, a byte can be read by 50ns. DQ pins serve as the ports for address and data
input/output as well as command inputs. Even the write-intensive systems can take advantage of FLASH′s extended reliability of
100K program/erase cycles with real time mapping-out algorithm. These algorithms have been implemented in many mass storage
applications.
In 128Mbit SDRAM, Synchronous design allows precise cycle control with the use of system clock, and I/O transactions are possible
on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high performance memory system applications.
The KAA00B606A is suitable for use in data memory of mobile communication system to reduce not only mount area but also power
consumption. This device is available in 127-ball TBGA Type.
-2-
Revision 1.0
May 2003
KAA00B606A
PIN DESCRIPTION
Pin Name
A0~A21
A0d~A11d
BA0~BA1
DQ0~DQ15
DQ0d~DQ15d
CEn
RE
WPn
ALE
CLE
R/Bn
WE
CSu
ZZu
UBu
LBu
OEu
CLK
Pin Function
Address Input(UtRAM)
Address Input(SDRAM)
Bank Address Input(SDRAM)
Data Input/Out Put(UtRAM, NAND)
Data Input/Out Put(SDRAM)
Chip Enable(NAND)
Read Enable(NAND)
Write Protection(NAND)
Address Latch Enable(NAND)
Command Latch Enable(NAND)
Read/Busy OutPut(NAND)
Write Enable(NAND, UtRAM)
Chip Enable(UtRAM)
Deep Power Down(UtRAM)
Upper Byte (UtRAM)
Low Byte(UtRAM)
Output Enable(UtRAM)
System Clock(SDRAM)
Pin Name
CSd
CKE
RAS
CAS
WEd
LDQM
UDQM
DPD
Vccn
Vccu
Vcc
Vccqn
Vccqu
Vccq
V
SS
NC
DNU
Preliminary
MCP MEMORY
Pin Function
Chip Enable(SDRAM)
Clock Enable(SDRAM)
Row Address Strobe(SDRAM)
Column Address Strobe(SDRAM)
Write Enable(SDRAM)
Low Data Out Put Mask(SDRAM)
Upper Data Out Put Mask(SDRAM)
Deep Power Down(SDRAM)
Power Supply(NAND)
Power Supply(UtRAM)
Power Supply(SDRAM)
Data Out Power(NAND)
Data Out Power(UtRAM)
Data Out Power(SDRAM)
Ground
No Connection
Do Not Use
ORDERING INFORMATION
KA A
Samsung
MCP Memory(3chips)
Device Type
NAND + UtRAM + SDRAM
NOR Flash Density, Voltage,
Organization, Bank Size, Boot Block
00 = None
00 B 6 0 6 A - T G P V/X
SDRAM Speed
V = 15ns
X = 10ns
UtRAM Speed
P = 85ns
NAND Flash Speed
G= 50ns
Package
T = TBGA
Version
A = 2nd Generation
DRAM Interface, Density, Voltage,
Organization, Option
6 = SDR, 128M, 1.8V/1.8V, X16, V
NAND Flash Density, Voltage, Organization
B = 256M, 1.8V/1.8V, X16
UtRAM Density, Voltage, Organization
6 = 64M, 3.0V/1.8V, X16
SRAM Density, Voltage, Organization
0 = None
-4-
Revision 1.0
May 2003
京公网安备 11010802033920号
EEWORLD
