ADVANCE INFORMATION
V
CCQ
REF
GND
2
1
FB
REF
Phase
Freq.
DET
Filter
VCO and
Time Unit
Generator
1Q0
1Q1
3F1
4F0
4F1
V
CCQ
V
CCN
4Q1
4Q0
GND
GND
5
6
7
8
9
10
11
12
13
3F0
FS
4
3
32 31
TEST
2F1
30
29
28
27
26
V
CCN
FB
V
CCN
3Q1
3Q0
1F0
1F1
1Q0
1Q1
1
2Q1
2Q0
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C39911/PI6C39912
3.3V High Speed LVTTL or Balanced Output
Programmable Skew Clock Buffer-SuperClock
Description
Features
All output pair skew <100ps typical (250 Max.)
3.75 MHz to 133 MHz output operation
User-selectable output functions
Selectable skew to 18ns
Inverted and Non-Inverted
Operation at ½ and ¼ input frequency
Operation at 2X and 4X input frequency
(input as low as 3.75 MHz)
Zero input-to-output delay
50% duty-cycle outputs
LVTTL outputs drive 50 Ohm terminated lines
Operates from a single 3.3V supply
Low operating current
32-pin PLCC package
Jitter < 200ps peak-to-peak (< 25ps RMS)
Available in LVTTL (PI6C39911) or Balanced (PI6C39912)
PI6C39911 is a pin-to-pin compatible with CY7B9911V
The PI6C39911 and PI6C39912 offer selectable control over system
clock functions. These multiple-output clock drivers provide the
system integrator with functions necessary to optimize the timing of
high-performance computer systems. Eight individual drivers, ar-
ranged as four pairs of user-controllable outputs, can each drive
terminated transmission lines with impedances as low as 50 Ohm
while delivering minimal and specified output skews and full-swing
logic levels.
Each output can be hardwired to one of nine delay or function
configurations. Delay increments of 0.7ns to 1.5ns are determined
by the operating frequency with outputs able to skew up to ±6 time
units from their nominal zero skew position. The completely
integrated PLL allows external load and transmission line delay
effects to be canceled. The user can create output-to-output delays
of up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided for
additional flexibility in designing complex clock systems. When
combined with the internal PLL, these divide functions allow distri-
bution of a low-frequency clock that can be multiplied by two or four
at the clock destination. This facility minimizes clock distribution
difficulty while allowing maximum system user-clock speed and
flexibility.
Logic Block Diagram
Test
Pin Configuration
4F0
4F1
Select Inputs
(three level)
4Q0
4Q1
Skew
Select
Matrix
3Q0
3Q1
2Q0
2Q1
2F0
GND
1F1
1F0
V
CCN
1Q0
1Q1
GND
GND
32-pin PLCC
25
24
23
22
21
3F0
3F1
2F0
2F1
14 15 16 17 18 19
20
PSXXXX
05/10/00
ADVANCE INFORMATION
PI6C39911/PI6C39912
3.3V High Speed LVTTL or Balanced Output
Programmable Skew Clock Buffer
- SuperClock
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Pin Descriptions
Signal Name
REF
FB
FS
1F0, 1F1
2F0, 2F1
3F0, 3F1
4F0, 4F1
TEST
1Q0, 1Q1
2Q0, 2Q1
3Q0, 3Q1
4Q0, 4Q1
V
CCN
V
CCQ
GND
I/O
I
I
I
I
I
I
I
I
O
O
O
O
PWR
PWR
De s cription
Reference frequency input. This input supplies the frequency and timing against which all functional variation is measured.
PLL feedback input (typically connected to one of the eight outputs)
Three- level frequency range select. see Table 1.
Three- level function select inputs for output pair 1 (1Q0, 1Q1). see Table 2.
Three- level function select inputs for output pair 2 (2Q0, 2Q1). see Table 2.
Three- level function select inputs for output pair 3 (3Q0, 3Q1). see Table 2.
Three- level function select inputs for output pair 4 (4Q0, 4Q1). see Table 2.
Three- level select. See test mode section under the block diagram descriptions
Output pair 1. see Table 2
Output pair 2. see Table 2
Output pair 3. see Table 2
Output pair 4. see Table 2
Power supply for output drivers
Power supply for internal circuitry
PWR Ground
Table 1. Frequency Range Select and t
U
Calculation
(1)
FS
(2,3)
LO W
MID
HIGH
F
NOM
(M Hz)
M in.
15
25
40
M ax.
30
50
133
t
U
=
f
NOM
× N
1
whe re N=
44
26
16
Approximate
Fre q. (M Hz) at
which t
U
= 1.0ns
22.7
38.5
62.5
2
PSXXXX
05/10/00
ADVANCE INFORMATION
PI6C39911/PI6C39912
3.3V High Speed LVTTL or Balanced Output
Programmable Skew Clock Buffer
- SuperClock
t
0
+1t
U
t
0
+2t
U
t
0
+3t
U
t
0
+4t
U
t
0
+5t
U
1Fx
2Fx
(N/A)
LL
LM
LH
ML
MM
MH
HL
HM
HH
FB Input
REF Input
3Fx
4Fx
LM
–6t
U
LH
(N/A)
ML
(N/A)
MM
(N/A)
MH
(N/A)
HL
–4t
U
–3t
U
–2t
U
–1t
U
0t
U
+1t
U
+2t
U
+3t
U
+4t
U
(N/A)
HM
+6t
U
(N/A) LL/HH Divided
(N/A)
HH Invert
Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output
(4)
Note:
4. FB connected to an output selected for
"zero" skew (ie., xF1 = xF0 = MID).
3
t
0
+6t
U
PSXXXX
t
0
–6t
U
t
0
–5t
U
t
0
–4t
U
t
0
–3t
U
t
0
–2t
U
t
0
–1t
U
t
0
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Table 2. Programmable Skew Configurations
(1)
Function Se le cts
1F1, 2F1,
3F1, 4F1
LO W
LO W
LO W
MID
MID
MID
HIGH
HIGH
HIGH
1F0, 2F0,
3F0, 4F0
LO W
MID
HIGH
LO W
MID
HIGH
LO W
MID
HIGH
Output Functions
1Q0, 1Q1,
2Q0, 2Q1
4t
U
3t
U
2t
U
1t
U
0t
U
+1t
U
+2t
U
+3t
U
+4t
U
3Q0, 3Q1
4Q0, 4Q1
Divide by 2 Divide by 2
6t
U
4t
U
2t
U
0t
U
+2t
U
+4t
U
+6t
U
Divide by 4
6t
U
4t
U
2t
U
0t
U
+2t
U
+4t
U
+6t
U
Inverted
Notes:
1. For all three-state inputs, HIGH indicates a connection to V
CC
,
LOW indicates a connection to GND, and MID indicates an open
connection. Internal termination circuitry holds an unconnected
input to V
CC
/2.
2. The level to be set on FS is determined by the normal operating
frequency (f
NOM
) of the V
CO
and Time Unit Generator (see Logic
Block Diagram). Nominal frequency (f
NOM
) always appears at
1Q0 and the other outputs when they are operated in their
undivided modes (see Table 2). The frequency appearing at the
REF and FB inputs will be f
NOM
when the output connected to
FB is undivided. The frequency of the REF and FB inputs will be
f
NOM
/2 or f
NOM
/4 when the part is configured for a frequency
multiplication by using a divided output as the FB input.
3. When the FS pin is selected HIGH, the REF input must not
transition upon power-up until V
CC
has reached 2.8V.
05/10/00
ADVANCE INFORMATION
PI6C39911/PI6C39912
3.3V High Speed LVTTL or Balanced Output
Programmable Skew Clock Buffer
- SuperClock
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Test Mode
The TEST input is a three-level input. In normal system operation,
this pin is connected to ground, allowing the PI6C39911 to operate
as explained briefly above (for testing purposes, any of the three
level inputs can have a removable jumper to ground, or be tied LOW
through a 100 Ohm resistor. This will allow an external tester to
change the state of these pins.)
If the TEST input is forced to its MID or HIGH state, the device will
operate with its internal phase locked loop disconnected, and input
levels supplied to REF will directly control all outputs. Relative
output to output functions are the same as in normal mode.
In contrast with normal operation (TEST tied LOW). All outputs
will function based only on the connection of their own function
select inputs (xF0 and xF1) and the waveform characteristics of the
REF input.
Maximum Ratings
Storage Temperature ...................................... 65°C to +150°C
Ambient Temperature with
Power Applied ................................................. 55°C to +125°C
Supply Voltage to Ground Potential .................. 0.5V to +5.0V
DC Input Voltage ............................................... 0.5V to +5.0V
Output Current into Outputs (LOW) ............................... 64mA
Static Discharge Voltage ............................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .........................................................>200mA
Operating Range
Range
Commercial
Industrial
Ambie nt Te mpe rature
0°C to +70°C
40°C to +85°C
V
CC
3.3V ±10%
3.3V ±10%
Capacitance
(10)
Parame te r
C
IN
D e s cription
Input Capacitance
Te s t Conditions
T
A
= 25°C, f = 1MHz, V
CC
= 3.3V
M ax.
10
Units
pF
AC Test Loads and Waveforms
TTL AC Test Load
V
CC
TTL Input Test Waveform
≤1ns
≤1ns
R1
3.0V
2.0V
Vth=1.5V
0.8V
0V
C
L
R2
R1=100
R2=100
C
L
=30pF
(Includes fixture and probe capacitance)
4
PSXXXX
05/10/00
ADVANCE INFORMATION
PI6C39911/PI6C39912
3.3V High Speed LVTTL or Balanced Output
Programmable Skew Clock Buffer
- SuperClock
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
Electrical Characteristics
(Over the Operating Range)
(5)
Parame te r
V
OH
V
OL
V
IH
V
IL
V
IHH
V
IMM
V
ILL
I
IH
I
IL
I
IHH
I
IMM
I
ILL
I
OS
I
CCQ
O utput HIGH Voltage
O utput LO W Voltage
Input HIGH Voltage (REF and FB inputs only)
Input LO W Voltage (REF and FB inputs only)
Three- Level Input HIGH Voltage (Test, FS, xFn)
(6)
Three- Level Input MID Voltage (Test, FS, xFn)
(6)
Three- Level Input LO W Voltage (Test, FS, xFn)
(6)
Min.
≤
V
CC
≤
Max.
Min.
≤
V
CC
≤
Max.
Min.
≤
V
CC
≤
Max.
D e s cription
Te s t Conditions
V
CC
= Min., I
OH
= 18mA
V
CC
= Min., I
OL
= 35mA
2.0
0.5
0.87
V
CC
0.47
V
CC
0.0
PI6C39911/PI6C39912
M in.
2.4
0.45
V
CC
0.8
V
CC
0.53
V
CC
0.13
V
CC
20
20
200
50
50
200
200
95
100
25
mA
mA
µA
V
M ax.
Units
Input HIGH Leakage Current (REF and FB inputs only) V
CC
= Max., V
IN
= Max.
Input LO W Leakage Current (REF and FB inputs only) V
CC
= Max., V
IN
= 0.4V
Input HIGH Current (Test, FS, xFn)
Input MID Current (Test, FS, xFn)
Input LO W Current (Test, FS, xFn)
Short Circuit Current
(7)
O perating Current Used by Internal Circuitry
V
IN
= V
CC
V
IN
= V
CC
/2
V
IN
=
GN D
V
CC
= Max., V
OUT
= GN D (25°C only)
V
CCN
= V
CCQ
= Max.,
All Input Selects O pen
V
CCN
= V
CCQ
= Max.,
I
OUT
= 0mA
All Input Selects O pen, f
MAX
V
CCN
= V
CCQ
= Max.,
I
OUT
= 0mA
All Input Selects O pen, f
MAX
Com'l
Mil/Ind
I
CCN
O utput Buffer Current per O utput
Pair
(8)
PD
Power Dissipation per O utput Pair
(9)
130
mW
Notes:
5. See the last page of this specification for Group A subgroup testing information.
6. These inputs are normally wired to V
CC
, GND, or left unconnected (actual threshold voltages vary as a percentage of V
CC
). Internal
termination resistors hold unconnected inputs at V
CC
/2. If these inputs are switched, the function and timing of the outputs may glitch
and the PLL may require an additional t
LOCK
time before all data sheet limits are achieved.
7. PI6C39911 should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle.
Room temperature only.
8. Total output current per output pair can be approximated by the following expression that includes device current plus load current:
PI6C39911:I
CCN
= [(4 + 0.11F) + [[((835 3F)/Z) + (.0022FC)]N] x 1.1
Where
F = frequency in MHz
C = capacitive load in pF
Z = line impedance in ohms
N = number of loaded outputs; 0, 1, or 2
FC = F < C
9. Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus
power dissipation due to the load circuit: PD = [(22 + 0.61F) + [[(1550 + 2.7F)/Z) + (.0125FC)]N] x 1.1 See note 8 for variable definition.
10. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters.
5
PSXXXX
05/10/00
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