MPC561RM/D
9/2003
REV 1
MPC561/MPC563 Reference Manual
Additional Devices Supported:
MPC562
MPC564
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© Motorola, Inc. 2003
MPC561RM/D 9/2003 REV 1
Contents
Paragraph
Section
Number
Title
About This Book
Audience ............................................................................................................ lxxv
Organization....................................................................................................... lxxv
Suggested Reading............................................................................................ lxxix
Conventions and Nomenclature......................................................................... lxxx
Notational Conventions .................................................................................... lxxxi
Acronyms and Abbreviations ........................................................................... lxxxi
References....................................................................................................... lxxxiii
Chapter 1
Overview
1.1
1.2
1.3
1.3.1
1.3.1.1
1.3.1.2
1.3.1.3
1.3.1.4
1.3.1.5
1.3.1.6
1.3.1.7
1.3.1.8
1.3.2
1.3.3
1.3.3.1
1.3.3.2
1.3.3.3
1.3.3.4
1.3.3.5
1.3.3.6
1.4
MOTOROLA
Page
Number
Introduction.......................................................................................................... 1-1
Block Diagram ..................................................................................................... 1-2
Key Features ........................................................................................................ 1-3
High-Performance CPU System ...................................................................... 1-3
RISC MCU Central Processing Unit (RCPU) ............................................. 1-4
Unified System Interface Unit (USIU) ........................................................ 1-4
Burst Buffer Controller (BBC) Module....................................................... 1-4
Flexible Memory Protection Unit................................................................ 1-5
Memory Controller ...................................................................................... 1-5
512-Kbytes of CDR3 Flash EEPROM Memory (UC3F) –
MPC563/MPC564 Only .......................................................................... 1-5
32-Kbyte Static RAM (CALRAM) ............................................................. 1-6
General Purpose I/O Support (GPIO).......................................................... 1-6
Nexus Debug Port (Class 3)............................................................................. 1-6
Integrated I/O System ...................................................................................... 1-6
Two Time Processor Units (TPU3).............................................................. 1-6
22-Channel Modular I/O System (MIOS14) ............................................... 1-7
Two Enhanced Queued Analog-to-Digital Converter Modules
(QADC64E)............................................................................................. 1-7
Three CAN 2.0B Controller (TouCAN) Modules ....................................... 1-7
Queued Serial Multi-Channel Module (QSMCM) ...................................... 1-8
Peripheral Pin Multiplexing (PPM) ............................................................. 1-8
MPC561/MPC563 Optional Features .................................................................. 1-9
Contents
iii
Contents
Paragraph
Number
1.5
1.6
1.7
1.8
1.9
Title
Page
Number
Comparison of MPC561/MPC563 and MPC555 ................................................ 1-9
Additional MPC561/MPC563 Differences........................................................ 1-10
SRAM Keep-Alive Power Behavior.................................................................. 1-11
MPC561/MPC563 Address Map ....................................................................... 1-12
Supporting Documentation List......................................................................... 1-14
Chapter 2
Signal Descriptions
2.1
2.2
2.2.1
2.2.2
2.3
2.4
2.5
2.5.1
2.5.2
2.5.3
2.6
2.6.1
2.6.2
2.6.3
2.6.4
2.6.4.1
2.6.4.2
2.6.4.3
2.6.4.4
2.6.5
Signal Groupings ................................................................................................. 2-1
Signal Summary................................................................................................... 2-3
MPC561/MPC563 Signal Multiplexing ........................................................ 2-20
READI Port Signal Sharing........................................................................... 2-21
Pad Module Configuration Register (PDMCR)................................................. 2-22
Pad Module Configuration Register (PDMCR2)............................................... 2-23
MPC561/MPC563 Development Support Signal Sharing................................. 2-26
JTAG Mode Selection.................................................................................... 2-27
BDM Mode Selection .................................................................................... 2-28
Nexus Mode Selection ................................................................................... 2-29
Reset State.......................................................................................................... 2-30
Signal Functionality Configuration Out of Reset .......................................... 2-30
Signal State During Reset .............................................................................. 2-30
Power-On Reset and Hard Reset ................................................................... 2-31
Pull-Up/Pull-Down ........................................................................................ 2-31
Pull-Up/Pull-Down Enable and Disable for 5-V Only and 2.6-V Only
Signals ................................................................................................... 2-31
Pull-Down Enable and Disable for 5-V/2.6-V Multiplexed Signals ......... 2-31
Special Pull Resistor Disable Control Functionality (SPRDS) ................. 2-32
Pull Device Select (PULL_SEL) ............................................................... 2-32
Signal Reset States......................................................................................... 2-32
Chapter 3
Central Processing Unit
3.1
3.2
3.3
3.4
3.4.1
3.4.2
3.4.3
3.4.4
iv
RCPU Block Diagram ......................................................................................... 3-2
RCPU Key Features............................................................................................. 3-3
Instruction Sequencer .......................................................................................... 3-3
Independent Execution Units............................................................................... 3-4
Branch Processing Unit (BPU) ........................................................................ 3-5
Integer Unit (IU) .............................................................................................. 3-6
Load/Store Unit (LSU) .................................................................................... 3-6
Floating-Point Unit (FPU) ............................................................................... 3-7
MPC561/MPC563 Reference Manual
MOTOROLA
Contents
Paragraph
Number
3.5
3.6
3.7
3.7.1
3.7.2
3.7.3
3.7.4
3.7.4.1
3.7.4.2
3.7.4.3
3.7.5
3.7.6
3.7.7
3.8
3.9
3.9.1
3.9.2
3.9.3
3.9.4
3.9.5
3.9.6
3.9.7
3.9.8
3.9.9
3.9.10
3.9.10.1
3.9.10.2
3.9.10.3
3.10
3.10.1
3.10.2
3.10.3
3.11
3.11.1
3.11.2
3.11.3
3.11.4
3.11.5
3.12
3.13
3.13.1
Title
Page
Number
Levels of the PowerPC ISA Architecture ............................................................ 3-7
RCPU Programming Model................................................................................. 3-8
User Instruction Set Architecture (UISA) Register Set ..................................... 3-13
General-Purpose Registers (GPRs)................................................................ 3-13
Floating-Point Registers (FPRs) .................................................................... 3-14
Floating-Point Status and Control Register (FPSCR).................................... 3-14
Condition Register (CR) ................................................................................ 3-17
Condition Register CR0 Field Definition .................................................. 3-18
Condition Register CR1 Field Definition .................................................. 3-18
Condition Register CRn Field — Compare Instruction ............................ 3-19
Integer Exception Register (XER)................................................................. 3-19
Link Register (LR)......................................................................................... 3-20
Count Register (CTR).................................................................................... 3-21
VEA Register Set — Time Base (TB) ............................................................... 3-21
OEA Register Set............................................................................................... 3-21
Machine State Register (MSR) ...................................................................... 3-21
DAE/Source Instruction Service Register (DSISR) ...................................... 3-24
Data Address Register (DAR) ....................................................................... 3-24
Time Base Facility (TB) — OEA .................................................................. 3-24
Decrementer Register (DEC)......................................................................... 3-24
Machine Status Save/Restore Register 0 (SRR0) .......................................... 3-25
Machine Status Save/Restore Register 1 (SRR1) .......................................... 3-25
General SPRs (SPRG0–SPRG3) ................................................................... 3-25
Processor Version Register (PVR)................................................................. 3-26
Implementation-Specific SPRs ...................................................................... 3-27
EIE, EID, and NRI Special-Purpose Registers.......................................... 3-27
Floating-Point Exception Cause Register (FPECR) .................................. 3-27
Additional Implementation-Specific Registers.......................................... 3-28
Instruction Set .................................................................................................... 3-28
Instruction Set Summary ............................................................................... 3-30
Recommended Simplified Mnemonics.......................................................... 3-35
Calculating Effective Addresses .................................................................... 3-35
Exception Model................................................................................................ 3-36
Exception Classes .......................................................................................... 3-37
Ordered Exceptions........................................................................................ 3-37
Unordered Exceptions.................................................................................... 3-37
Precise Exceptions ......................................................................................... 3-38
Exception Vector Table .................................................................................. 3-38
Instruction Timing.............................................................................................. 3-40
User Instruction Set Architecture (UISA) ......................................................... 3-42
Computation Modes....................................................................................... 3-42
MOTOROLA
Contents
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