EEWORLDEEWORLDEEWORLD

Part Number

Search

V826632G24SATG-D3

Description
DDR DRAM Module, 32MX64, 0.65ns, CMOS, PDMA200
Categorystorage    storage   
File Size250KB,15 Pages
ManufacturerProMOS Technologies Inc
Download Datasheet Parametric View All

V826632G24SATG-D3 Overview

DDR DRAM Module, 32MX64, 0.65ns, CMOS, PDMA200

V826632G24SATG-D3 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerProMOS Technologies Inc
Reach Compliance Codecompliant
Maximum access time0.65 ns
Maximum clock frequency (fCLK)200 MHz
I/O typeCOMMON
JESD-30 codeR-PDMA-N200
JESD-609 codee4
memory density2147483648 bit
Memory IC TypeDDR DRAM MODULE
memory width64
Number of terminals200
word count33554432 words
character code32000000
Maximum operating temperature70 °C
Minimum operating temperature
organize32MX64
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeDIMM
Encapsulate equivalent codeDIMM200,24
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply2.6 V
Certification statusNot Qualified
refresh cycle8192
Maximum slew rate3.2 mA
Nominal supply voltage (Vsup)2.6 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceGOLD
Terminal formNO LEAD
Terminal pitch0.6 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
V826632G24SA
256 MB 200-PIN DDR UNBUFFERED SODIMM
32M x 64
Features
JEDEC 200 Pin DDR Unbuffered Small-Outline,
Dual In-Line memory module (SODIMM);
33,554,432 x 64 bit organization.
Utilizes High Performance 32M x 8 DDR
SDRAM in TSOPII-66 Packages
Single +2.5V (± 0.2V) Power Supply
Single +2.6V (± 0.1V) Power Supply for DDR400
Programmable CAS Latency, Burst Length, and
Wrap Sequence (Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All Inputs, Outputs are SSTL-2 Compatible
8192 Refresh Cycles every 64 ms
Serial Presence Detect (SPD)
Module Speed
t
CK
A1
t
AC
B0
B1
t
AC
C0
t
AC
Description
The V826632G24SA memory module is
organized 33,554,432 x 64 bits in a 200 pin memory
module. The 32M x 64 memory module uses 8
ProMOS 32M x 8 DDR SDRAM. The x64 modules
are ideal for use in high performance computer
systems where increased memory density and fast
access times are required.
D4
D3
D0
C0
B1
B0
A1
Units
Clock Frequency
200
200
166
143
133
125
MHz
Module Speed
200
(PC400C) (PC400B) (PC400A) (PC333) (PC266A) (PC266B) (PC200)
(max.)
PC1600 (100MHz @ CL2)
Clock Cycle Time
7.5
7.5
7.5
7.5
10
10
ns
PC2100B (133MHz @ CL2.5) 7.5
CAS Latency = 2
PC2100A (133MHz @ CL2)
Clock Cycle Time
6
6
5
6
7
7.5
8
ns
PC2700 (166MHz @ CL2.5)
CAS Latency = 2.5
Clock Cycle Time
CAS Latency = 3
5
5
5
-
-
-
-
ns
t
RCD
tRP parameter
t
RP
tRCD parameter
4
4
3
3
3
3
3
3
2
2
3
3
2
2
CLK
CLK
V826632G24SA Rev. 1.1 February 2004
1

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1002  2351  418  1563  2262  21  48  9  32  46 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号