ICS9250YF-51LF-T datasheet, PDF

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ICS9250YF-51LF-T: DescriptionProcessor Specific Clock Generator, 133MHz, PDSO56, 0.300 INCH, SSOP-56; CategoryThe embedded processor and controller Microcontrollers and processors; File Size227KB，14 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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ICS9250YF-51LF-T Overview

Processor Specific Clock Generator, 133MHz, PDSO56, 0.300 INCH, SSOP-56

ICS9250YF-51LF-T Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	SSOP
package instruction	SSOP,
Contacts	56
Reach Compliance Code	compliant
ECCN code	EAR99
JESD-30 code	R-PDSO-G56
JESD-609 code	e3
length	18.415 mm
Number of terminals	56
Maximum operating temperature	70 °C
Minimum operating temperature
Maximum output clock frequency	133 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	SSOP
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260
Master clock/crystal nominal frequency	16 MHz
Certification status	Not Qualified
Maximum seat height	2.794 mm
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	7.5 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC

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Integrated

Circuit

Systems, Inc.

ICS9250-51

Frequency Generator & Integrated Buffers for Celeron & PII/III™

Recommended Application:

815 B-Step type chipset.

Output Features:

•

3 CPU (2.5V) (up to 133MHz achievable through

•

9 SDRAM (3.3V) (up to 133MHz achievable

through I

•

7 PCI (3.3 V) @33.3MHz

•

2 IOAPIC (2.5V) @ 33.3 MHz

•

3 Hublink clocks (3.3 V) @ 66.6 MHz

•

2 (3.3V) @ 48 MHz (Non spread spectrum)

•

1 REF (3.3V) @ 14.318 MHz

Features:

•

Supports spread spectrum modulation,

0 to -0.5% down spread.

•

C support for power management

•

Efficient power management scheme through PD#

•

Uses external 14.138 MHz crystal

•

Alternate frequency selections available through I

control.

•

815 B-Step compliant for frequency select latched

inputs. Internal power-on-reset and latching, are

delayed until Vtt_PWRGD signal is gated high onto

the PD#.

Pin Configuration

*FS2//REF0

VDD

GND

3V66-0

3V66-1

3V66-2

VDD

PCICLK_F

PCICLK0

GND

PCICLK1

PCICLK2

GND

PCICLK3

PCICLK4

PCICLK5

VDD

AVDD

AGND

GND

48MHz_0

48MHz_1

VDD48

FS0

GNDL

IOAPIC0

IOAPIC1

VDDL

CPUCLK0

VDDL0

CPUCLK1

CPUCLK2

GNDL

GND

SDRAM0

SDRAM1

VDD

SDRAM2

SDRAM3

GND

SDRAM4

SDRAM5

VDD

SDRAM6

SDRAM7

GND

SDRAM_F

VDD

Vtt_PWRGD/PD#

SCLK

SDATA

FS1

56-Pin 300mil SSOP

* This input has a 50KΩ pull-down to GND.

Block Diagram

XTAL

OSC

PLL1

Spread

Spectrum

REF0

Functionality

FS2

FS1

FS0

ICS9250-51

Function

Tristate

Test

Active CPU = 66MHz

SDRAM = 100MHz

Active CPU = 100MHz

SDRAM = 100MHz

Active CPU = 133MHz

SDRAM = 133MHz

Active CPU = 133MHz

SDRAM = 100MHz

VDDL

CPU66/100/133 (2:0)

3V66 (2:0)

SDRAM (7:0)

SDRAM_F

PCICLK (5:0)

PCICLK_F

FS (2:0)

PD#

Vtt_PWRGD

SDATA

SCLK

Control

Logic

Config

Reg

PLL2

IOAPIC (1:0)

VDDL

48MHz (1:0)

Power Groups

AVDD = Pin 22 Analog power for PLL

AGND = Pin 23 Analog ground

VDD48 = Pin 27 Analog power for 48MHz PLL

GND48 = Pin 24 Analog ground for 48MHz PLL

0405A—03/22/02

ICS9250YF-51LF-T Related Products

	ICS9250YF-51LF-T	ICS9250YF-51-T
Description	Processor Specific Clock Generator, 133MHz, PDSO56, 0.300 INCH, SSOP-56	Processor Specific Clock Generator, 133MHz, PDSO56, 0.300 INCH, SSOP-56
Is it lead-free?	Lead free	Contains lead
Is it Rohs certified?	conform to	incompatible
Parts packaging code	SSOP	SSOP
package instruction	SSOP,	SSOP,
Contacts	56	56
Reach Compliance Code	compliant	compliant
ECCN code	EAR99	EAR99
JESD-30 code	R-PDSO-G56	R-PDSO-G56
JESD-609 code	e3	e0
length	18.415 mm	18.415 mm
Number of terminals	56	56
Maximum operating temperature	70 °C	70 °C
Maximum output clock frequency	133 MHz	133 MHz
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	SSOP	SSOP
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	260	225
Master clock/crystal nominal frequency	16 MHz	16 MHz
Certification status	Not Qualified	Not Qualified
Maximum seat height	2.794 mm	2.794 mm
Maximum supply voltage	3.465 V	3.465 V
Minimum supply voltage	3.135 V	3.135 V
Nominal supply voltage	3.3 V	3.3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal surface	Matte Tin (Sn)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	GULL WING
Terminal pitch	0.635 mm	0.635 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	30	30
width	7.5 mm	7.5 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, PROCESSOR SPECIFIC	CLOCK GENERATOR, PROCESSOR SPECIFIC

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