selection of one of two different frequencies stored
in memory.
The device also has an power down feature that
tri states the clock outputs and turns off the PLL
when the PDTS pin is taken low.
This data sheet is to be used with the one-page
programming information for the complete
specification on the device.
Block Diagram
SEL
OTP
ROM
with PLL
Divider
Values
PLL
Clock
Synthesis
and Control
Circuitry
Output
Buffer
CLK2
X1/ICLK
5-27 MHz
crystal or
clock
Crystal
Oscillator
X2
Output
Buffer
CLK1
PDTS (both outputs and PLL)
Optional crystal capacitors
MDS 332 A
1
Revision 011601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel • www.icst.com
PRELIMINARY INFORMATION
ICS332
QTClock™ Dual Output Clock
Pin Assignment
X1/ICLK
VDD
GND
CLK1
1
2
3
4
8
7
6
5
X2
PDTS
SEL
CLK2
Output
Select Table
SEL
0
1
CLK1 (MHz)
TBD
TBD
CLK2 (MHz)
TBD
TBD
Spread Amount
TBD
TBD
The select pin can also be defined as a power
down or tri state for a single clock.
Pin Descriptions
Number
1
2
3
4
5
6
7
8
Name
X1/ICLK
VDD
GND
CLK1
CLK2
SEL
PDTS
X2
Type
XI
P
P
O
O
I
I
XO
Description
Crystal connection. Connect to an 5 to 27 MHz fundamental crystal or clock input.
Connect to +3.3 V.
Connect to ground.
Clock 1 output. Can be same frequency as crystal, or a divide from the PLL.
CMOS level clock output. Weak internal pull-down when tri state.
Select pin for frequency selection on CLK1 and CLK2. Internal pull-up.
Powers down entire chip, tri states CLK1 and CLK2 outputs, when low. Internal pull-up.
Crystal connection. Connect to an 5 to 27 MHz fundamental crystal. Float for clock.
Key: XI/XO = Crystal Connections, I = Input, O = output, P = power supply connection
External Components / Crystal Selection
The ICS332 requires a 0.01µF decoupling capacitor to be connected between VDD and GND. It must be
connected close to the ICS332 to minimize lead inductance. No external power supply filtering is required
for this device. A 33
Ω
terminating resistor can be used next to each output pin. A parallel resonant,
fundamental mode crystal should be used. Crystal capacitors should be connected from each of the pins
X1 and X2 to Ground as shown in the Block Diagram on page 1. The value (in pF) of these crystal caps
should be = (CL -6)*2, where CL is the crystal load capacitance in pF. These external capacitors are
required for all applications.
MDS 332 A
2
Revision 011601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel • www.icst.com
PRELIMINARY INFORMATION
ICS332
QTClock™ Dual Output Clock
Typical
Maximum
7
VDD+0.5
VDD+0.5
70
260
150
3.47
0.4
(VDD/2)-1
Units
V
V
V
°C
°C
°C
V
V
V
V
V
V
V
V
mA
mA
kΩ
pF
MHz
MHz
MHz
ppm
ns
ns
%
µs
µs
ps
ps
Electrical Specifications
Parameter
Conditions
Minimum
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, VDD
Referenced to GND
Inputs
Referenced to GND
-0.5
Clock Outputs
Referenced to GND
-0.5
Ambient Operating Temperature
0
Soldering Temperature
Max of 10 seconds
Storage temperature
-65
DC CHARACTERISTICS (VDD = 3.3V unless otherwise noted)
Operating Voltage, VDD
3.13
Input High Voltage, VIH
PDTS, SEL
2
Input Low Voltage, VIL
PDTS, SEL
Input High Voltage, VIH
ICLK
(VDD/2)+1
Input Low Voltage, VIL
ICLK
Output High Voltage, VOH, CMOS high
IOH=-8mA
VDD-0.4
Output High Voltage, VOH
IOH=-12mA
2.4
Output Low Voltage, VOL
IOL=12mA
IDD Operating Supply Current
No Load
Short Circuit Current
Outputs
On-Chip Pull-up Resistor
Input pins
Input Capacitance
Input pins
AC CHARACTERISTICS (VDD = 3.3V unless otherwise noted)
Input Frequency, crystal input
5
Input Frequency, clock input
3
Output Frequency
TBD
(Depends on programming)
Output Frequency Synthesis Error
Output Clock Rise Time
0.8 to 2.0V
Output Clock Fall Time
2.0 to 0.8V
Output Clock Duty Cycle
at VDD/2
45
Output Enable Time, PDTS high to output on
Output Disable Time, PDTS low to tri state
Absolute Clock Period Jitter
Deviation from mean
One Sigma Clock Period Jitter
0.4
TBD
±70
270
7
27
50
200
TBD
0
1
1
49 to 51
55
TBD
TBD
TBD
TBD
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure
to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. Typical values are at 25°C.
MDS 332 A
3
Revision 011601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel • www.icst.com
PRELIMINARY INFORMATION
ICS332
QTClock™ Dual Output Clock
Package Outline and Package Dimensions
(
For current dimensional specifications, see JEDEC Publication No. 95.)
8 pin SOIC
Symbol
A
A1
E
INDEX
AREA
H
B
C
1
D
A1
e
B
C
h x 45°
D
E
e
H
h
L
Inches
Min
Max
0.0532 0.0688
0.0040 0.0098
0.0130 0.0200
0.0075 0.0098
0.1890 0.1968
0.1497 0.1574
.050 BSC
0.2284 0.2440
0.0099 0.0195
0.0160 0.0500
Millimeters
Min
Max
1.35
1.75
0.10
0.24
0.33
0.51
0.19
0.24
4.80
5.00
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.41
1.27
A
L
Ordering Information
Part/Order Number
ICS332M-xx
ICS332M-xxT
Marking
ICS332M
ICS332M
Package
8 pin SOIC
8 pin SOIC on tape and reel
Temperature
0 to 70 °C
0 to 70 °C
The -xx indicates a two-character programming code, which must be specified when
ordering parts.
While the information presented herein has been checked for both accuracy and reliability, ICS assumes no responsibility for either its use or for the infringement of any patents or
other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications.
Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life
support devices or critical medical instruments.
MDS 332 A
4
Revision 011601
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel • www.icst.com
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