Pipeline Register, 16-Bit, CMOS, CDIP48, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-48
| Parameter Name | Attribute value |
| Is it Rohs certified? | incompatible |
| Maker | IDT (Integrated Device Technology) |
| Parts packaging code | DIP |
| package instruction | 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-48 |
| Contacts | 48 |
| Reach Compliance Code | not_compliant |
| ECCN code | 3A001.A.3 |
| boundary scan | NO |
| maximum clock frequency | 66.67 MHz |
| External data bus width | 16 |
| JESD-30 code | R-CDIP-T48 |
| JESD-609 code | e0 |
| length | 60.96 mm |
| low power mode | NO |
| Number of terminals | 48 |
| Maximum operating temperature | 70 °C |
| Minimum operating temperature | |
| Output data bus width | 16 |
| Package body material | CERAMIC, METAL-SEALED COFIRED |
| encapsulated code | DIP |
| Encapsulate equivalent code | DIP48,.6 |
| Package shape | RECTANGULAR |
| Package form | IN-LINE |
| Peak Reflow Temperature (Celsius) | NOT SPECIFIED |
| power supply | 5 V |
| Certification status | Not Qualified |
| Maximum seat height | 4.826 mm |
| Maximum supply voltage | 5.5 V |
| Minimum supply voltage | 4.5 V |
| Nominal supply voltage | 5 V |
| surface mount | NO |
| technology | CMOS |
| Temperature level | COMMERCIAL |
| Terminal surface | Tin/Lead (Sn/Pb) |
| Terminal form | THROUGH-HOLE |
| Terminal pitch | 2.54 mm |
| Terminal location | DUAL |
| Maximum time at peak reflow temperature | NOT SPECIFIED |
| width | 15.24 mm |
| uPs/uCs/peripheral integrated circuit type | DSP PERIPHERAL, PIPELINE REGISTER |
京公网安备 11010802033920号
EEWORLD
