EEWORLDEEWORLDEEWORLD

Part Number

Search

531UA600M000DG

Description
CMOS/TTL Output Clock Oscillator, 600MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
CategoryPassive components    oscillator   
File Size215KB,12 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

531UA600M000DG Overview

CMOS/TTL Output Clock Oscillator, 600MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

531UA600M000DG Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
Objectid1596220963
Reach Compliance Codeunknown
compound_id68525378
Other featuresTRAY
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability50%
JESD-609 codee4
Manufacturer's serial number531
Installation featuresSURFACE MOUNT
Nominal operating frequency600 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeCMOS/TTL
physical size7.0mm x 5.0mm x 1.85mm
longest rise time0.35 ns
Maximum supply voltage2.75 V
Minimum supply voltage2.25 V
Nominal supply voltage2.5 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
S i 5 3 0 / 5 31
R
EVISION
D
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si530/531
A new round of TI technical seminars is about to begin! (August 2-11) - Added detailed schedule
Haha, MCU DAY seems not to have ended yet, TI's new seminar has begun again. Haha, everyone has more opportunities to discuss related technologies and products face to face with TI engineers.TI has pr...
soso MCU
Design of Image Acquisition System Based on FPGA and CCD
Hello brothers and sisters, I am currently working on a project to design an image acquisition system based on FPGA and CCD. However, after looking at the datasheet of the area array CCD, I feel that ...
wxq20061001 Embedded System
Welcome our new moderator lugl4313820 of the Guoxin section~
Our Guoxin section has a new moderator~~@lugl4313820 Welcome to join the EEWorld moderator team~~ Let's work together to create a better EEWorld forum~~~~...
okhxyyo Talking
Recruitment: One hardware engineer, Location: Shenzhen
Requirements for the position of embedded hardware development engineer: 1. Bachelor degree or above; 2. Major in electronics/radio communication/computer; 3. Familiar with electronics, software and m...
wlzwlz777 Embedded System
Why can't I use the peripheral library in my program?
#include "lm3s3739.h" #include "hw_sysctl.h"#include "hw_types.h"#include "hw_comp.h"#include "hw_gpio.h"#include "hw_ints.h"#include "hw_memmap.h"#include "hw_nvic.h"#include "hw_timer.h" I have incl...
yuchenglin Microcontroller MCU
FPGA learning board, Red Hurricane, 550, used by myself, now selling,
A learning board for beginners, with basic experiments included, it's easy to use. If you have friends who want to learn FPGA, I can give you some good information....
lxwljf2004 FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2241  2927  44  80  1203  46  59  1  2  25 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号