ATtiny20
8-bit AVR Microcontroller
with 2K Bytes In-System Programmable Flash
DATASHEET
Features
High performance, low power 8-bit AVR
®
microcontroller
Advanced RISC architecture
112 powerful instructions – most single clock cycle execution
16 x 8 general purpose working registers
Fully static operation
Up to 12 MIPS throughput at 12MHz
2K bytes of in-system programmable flash program memory
128 bytes internal SRAM
Flash write/erase cycles: 10,000
Data retention: 20 years at 85
o
C / 100 years at 25
o
C
One 8-bit timer/counter with two PWM channels
One 16-bit timer/counter with two PWM channels
10-bit analog to digital converter
8 single-ended channels
Programmable watchdog timer with separate on-chip oscillator
On-chip analog comparator
Master/slave SPI serial interface
Slave TWI serial interface
In-system programmable
External and internal interrupt sources
Low power idle, ADC noise reduction, stand-by and power-down modes
Enhanced power-on reset circuit
Internal calibrated oscillator
14-pin SOIC/TSSOP: 12 programmable I/O lines
12-ball WLCSP: 10 programmable I/O lines
15-ball UFBGA: 12 programmable I/O lines
20-pad VQFN: 12 programmable I/O lines
1.8 – 5.5V
5V
Non-volatile program and data memories
Peripheral features
Special microcontroller features
I/O and packages
Operating voltage:
Programming voltage:
Speed grade
0 – 4MHz @ 1.8 – 5.5V
0 – 8MHz @ 2.7 – 5.5V
0 – 12MHz @ 4.5 – 5.5V
Industrial temperature range
Low power consumption
Active mode:
200
μA
at 1MHz and 1.8V
Idle mode:
25μA at 1MHz and 1.8V
Power-down mode:
< 0.1μA at 1.8V
8235E–AVR–03/2013
1.
1.1
Pin Configurations
SOIC & TSSOP
Figure 1-1. SOIC/TSSOP
VCC
(PCINT8/TPICLK/T0/CLKI) PB0
(PCINT9/TPIDATA/MOSI/SDA/OC1A) PB1
(PCINT11/RESET) PB3
(PCINT10/INT0/MISO/OC1B/OC0A/CKOUT) PB2
(PCINT7/SCL/SCK/T1/ICP1/OC0B/ADC7) PA7
(PCINT6/SS/ADC6) PA6
1
2
3
4
5
6
7
14
13
12
11
10
9
8
GND
PA0 (ADC0/PCINT0)
PA1 (ADC1/AIN0/PCINT1)
PA2 (ADC2/AIN1/PCINT2)
PA3 (ADC3/PCINT3)
PA4 (ADC4/PCINT4)
PA5 (ADC5/PCINT5)
1.2
VQFN
Figure 1-2. VQFN
20
19
18
17
16
DNC
DNC
DNC
PA5 (ADC5/PCINT5)
PA6 (ADC6/PCINT6/SS)
NOTE
Bottom pad should be
soldered to ground.
DNC: Do Not Connect
DNC
DNC
GND
VCC
DNC
10
(PCINT4/ADC4) PA4
(PCINT3/ADC3) PA3
(PCINT2/AIN1/ADC2) PA2
(PCINT1/AIN0/ADC1) PA1
(PCINT0/ADC0) PA0
1
2
3
4
5
6
7
8
9
15
14
13
12
11
PA7 (ADC7/OC0B/ICP1/T1/SCL/SCK/PCINT7)
PB2 (CKOUT/OC0A/OC1B/MISO/INT0/PCINT10)
PB3 (RESET/PCINT11)
PB1 (OC1A/SDA/MOSI/TPIDATA/PCINT9)
PB0 (CLKI/T0/TPICLK/PCINT8)
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
2
1.3
UFBGA
Figure 1-3. UFBGA
1
A
B
C
D
2
3
4
4
3
2
1
A
B
C
D
TOP VIEW
BOTTOM VIEW
Table 1-1.
UFBGA Pin Configuration
1
A
B
C
D
PA4
PA3
PA0
2
PA5
PA7
PA2
GND
3
PA6
PB1
PA1
GND
4
PB2
PB3
PB0
VCC
1.4
Wafer Level Chip Scale Package
Figure 1-4. WLCSP
1
A
B
C
D
2
3
4
6 5 4 3 2 1
A
B
C
D
TOP VIEW
BOTTOM VIEW
Table 1-2.
WLCSP Ball Configuration
1
2
3
PA1
PA6
PA5
PB2
PA7
PB3
GND
PB1
PB0
4
5
PA2
VDD
6
A
B
C
D
PA4
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
3
1.5
1.5.1
Pin Description
VCC
Supply voltage.
1.5.2
GND
Ground.
1.5.3
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not
running and provided the reset pin has not been disabled. The minimum pulse length is given in
Table 20-4 on page 170.
Shorter pulses are not guaranteed to generate a reset.
The reset pin can also be used as a (weak) I/O pin.
1.5.4
Port A (PA7:PA0)
Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have
symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally
pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition
becomes active, even if the clock is not running.
Port A has alternate functions as analog inputs for the ADC, analog comparator and pin change interrupt as described in
“Alternate Port Functions” on page 47.
1.5.5
Port B (PB3:PB0)
Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have
symmetrical drive characteristics with both high sink and source capability except PB3 which has the RESET capability.
To use pin PB3 as an I/O pin, instead of RESET pin, program (‘0’) RSTDISBL fuse. As inputs, Port B pins that are
externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset
condition becomes active, even if the clock is not running.
The port also serves the functions of various special features of the ATtiny20, as listed on
page 37.
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
4
2.
Overview
ATtiny20 is a low-power CMOS 8-bit microcontroller based on the compact AVR enhanced RISC architecture. By
executing powerful instructions in a single clock cycle, the ATtiny20 achieves throughputs approaching 1 MIPS per MHz
allowing the system designer to optimize power consumption versus processing speed.
Figure 2-1. Block Diagram
V
CC
RESET
PROGRAMMING
LOGIC
PROGRAM
COUNTER
INTERNAL
OSCILLATOR
CALIBRATED
OSCILLATOR
PROGRAM
FLASH
STACK
POINTER
WATCHDOG
TIMER
TIMING AND
CONTROL
INSTRUCTION
REGISTER
SRAM
RESET FLAG
REGISTER
INSTRUCTION
DECODER
INTERRUPT
UNIT
MCU STATUS
REGISTER
CONTROL
LINES
GENERAL
PURPOSE
REGISTERS
X
Y
Z
TIMER/
COUNTER0
TIMER/
COUNTER1
ALU
SPI
ANALOG
COMPARATOR
ISP
INTERFACE
STATUS
REGISTER
TWI
ADC
8-BIT DATA BUS
DATA REGISTER
PORT A
DIRECTION
REG. PORT A
DATA REGISTER
PORT B
DIRECTION
REG. PORT B
DRIVERS
PORT A
DRIVERS
PORT B
PA[7:0]
GND
PB[3:0]
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
5
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