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2SK3948G-U

Description
Small Signal Field-Effect Transistor, 0.00047A I(D), 20V, 1-Element, N-Channel, Silicon, Junction FET, ROHS COMPLIANT, TSSSMINI3-F2, 3 PIN
CategoryDiscrete semiconductor    The transistor   
File Size407KB,4 Pages
ManufacturerPanasonic
Websitehttp://www.panasonic.co.jp/semicon/e-index.html
Environmental Compliance
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2SK3948G-U Overview

Small Signal Field-Effect Transistor, 0.00047A I(D), 20V, 1-Element, N-Channel, Silicon, Junction FET, ROHS COMPLIANT, TSSSMINI3-F2, 3 PIN

2SK3948G-U Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
package instructionSMALL OUTLINE, R-PDSO-F3
Contacts3
Reach Compliance Codeunknow
ECCN codeEAR99
Other featuresLOW NOISE
ConfigurationSINGLE
Minimum drain-source breakdown voltage20 V
Maximum drain current (ID)0.00047 A
FET technologyJUNCTION
JESD-30 codeR-PDSO-F3
Number of components1
Number of terminals3
Operating modeDEPLETION MODE
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Polarity/channel typeN-CHANNEL
Certification statusNot Qualified
surface mountYES
Terminal formFLAT
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
transistor applicationsSWITCHING
Transistor component materialsSILICON
Base Number Matches1
This product complies with the RoHS Directive (EU 2002/95/EC).
Silicon Junction FETs (Small Signal)
2SK3948
Silicon N-channel junction FET
For impedance conversion in low frequency
For electret capacitor microphone
Features
Low noise voltage NV
High voltage gain GV
Thin package: TSSSMini3-F1 (1.2 mm
×
1.2 mm
×
0.33 mm)
Package
Code
TSSSMini3-F1
Name
Pin
1: Drain
2: Source
3: Gate
Drain-source voltage (Gate open)
Drain-source current (Gate open)
Power dissipation
V
DSO
I
DSO
P
D
Drain-gate voltage (Souece open)
Drain-gate current (Souece open)
Operating ambient temperature
Storage temperature
V
DGO
I
DGO
T
opr
T
stg
–20 to +80
–55 to +125
Electrical Characteristics
T
a
= 25°C±3°C
Parameter
Drain current
*1
I
D
Symbol
I
DSS
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/ ion
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20
20
2
2
V
V
M
ain
Di
sc te
on na
tin nc
ue e/
d
Absolute Maximum Ratings
T
a
= 25°C
Parameter
Symbol
Rating
Unit
mA
mA
°C
°C
100
mW
Conditions
V
DD
= 2.0 V, R
d
= 2.2 kW
±
1%
Drain-source current
*2
Mutual conductance
Noise voltage
*3
V
DD
= 2.0 V, R
d
= 2.2 kW
±
1%, V
GS
= 0
V
DS
= 2.0 V, V
GS
= 0, f = 1 kHz
V
DD
= 2.0 V, R
d
= 2.2 kW
±
1%
C
O
= 5 pF, A-curve
Marking Symbol: 4X
Min
170
180
660
Typ
Max
470
450
Unit
mA
mA
mS
mV
di
isc
on
NV
tin
ue
1 500
8
ce
/D
G
V1
G
V2
G
V3
V
DD
= 2.0 V, R
d
= 2.2 kW
±
1%
C
O
= 5 pF, e
G
= 10 mV, f = 1 kHz
–5.0
–1.0
3.0
Ma
int
en
Voltage gain
V
DD
= 12 V, R
d
= 2.2 kW
±
1%
C
O
= 5 pF, e
G
= 10 mV, f = 1 kHz
V
DD
= 1.5 V, R
d
= 2.2 kW
±
1%
C
O
= 5 pF, e
G
= 10 mV, f = 1 kHz
V
DD
= 2.0 V, R
d
= 2.2 kW
±
1%
C
O
= 5 pF, e
G
= 10 mV
f = 1 kHz to 70 Hz
an
–3.0
–7.0
–1.5
dB
Voltage gain difference
DG
V
. f
*4
Pl
0.0
0.5
1.7
1.0
dB
G
V1
– G
V3
Note) 1. Measuring methods are based on JAPANESE INDUSTRIAL STANDARD JIS C 7030 measuring methods for transistors.
2. A protection diode is built-in between gate and source of transistor. However if forward current
flows
between gate and source transistor
might be damaged. So please be careful not insert reverse.
3. *1: I
D
is assured for I
DSS
.
*2: Rank classification
Rank
I
D
(mA)
I
DSS
(mA)
T
170 to 330
180 to 320
U
270 to 470
280 to 450
*3: NV is assured for design.
*4:
D|G
V
. f
|
is assured for AQL 0.065. (The measurement method is used by source-grounded circuit.)
Publication date: August 2008
SJF00097CED
1

2SK3948G-U Related Products

2SK3948G-U 2SK3948G-T
Description Small Signal Field-Effect Transistor, 0.00047A I(D), 20V, 1-Element, N-Channel, Silicon, Junction FET, ROHS COMPLIANT, TSSSMINI3-F2, 3 PIN Small Signal Field-Effect Transistor, 0.00033A I(D), 20V, 1-Element, N-Channel, Silicon, Junction FET, ROHS COMPLIANT, TSSSMINI3-F2, 3 PIN
Is it Rohs certified? conform to conform to
package instruction SMALL OUTLINE, R-PDSO-F3 SMALL OUTLINE, R-PDSO-F3
Contacts 3 3
Reach Compliance Code unknow unknow
ECCN code EAR99 EAR99
Other features LOW NOISE LOW NOISE
Configuration SINGLE SINGLE
Minimum drain-source breakdown voltage 20 V 20 V
Maximum drain current (ID) 0.00047 A 0.00033 A
FET technology JUNCTION JUNCTION
JESD-30 code R-PDSO-F3 R-PDSO-F3
Number of components 1 1
Number of terminals 3 3
Operating mode DEPLETION MODE DEPLETION MODE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
Package shape RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE SMALL OUTLINE
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED
Polarity/channel type N-CHANNEL N-CHANNEL
Certification status Not Qualified Not Qualified
surface mount YES YES
Terminal form FLAT FLAT
Terminal location DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED
transistor applications SWITCHING SWITCHING
Transistor component materials SILICON SILICON
Base Number Matches 1 1
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