LM3S102-IRN20 datasheet, PDF - EEWORLD Datasheet

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LM3S102-IRN20: DescriptionMicrocontroller,; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，335 Pages; ManufacturerLuminary Micro

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LM3S102-IRN20 Overview

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LM3S102-IRN20 Parametric

Parameter Name	Attribute value
Maker	Luminary Micro
package instruction	,
Reach Compliance Code	unknown

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P RE L I M I NA R Y

LM3S102 Microcontroller

D A TA SH EET

DS -LM3S 102- 04

LM3S102 Data Sheet

Table of Contents

Legal Disclaimers and Trademark Information.............................................................................. 2

Revision History ............................................................................................................................. 15

About This Document..................................................................................................................... 16

Audience........................................................................................................................................................... 16

About This Manual............................................................................................................................................ 16

Related Documents .......................................................................................................................................... 16

Documentation Conventions............................................................................................................................. 16

1.1

1.2

1.3

1.4

1.4.1

1.4.2

1.4.3

1.4.4

1.4.5

1.4.6

1.4.7

1.4.8

1.5

Architectural Overview ....................................................................................................... 19

Product Features ................................................................................................................................. 19

Target Applications .............................................................................................................................. 22

High-Level Block Diagram ................................................................................................................... 23

Functional Overview ............................................................................................................................ 24

ARM Cortex™-M3 ............................................................................................................................... 24

Motor Control Peripherals .................................................................................................................... 24

Analog Peripherals .............................................................................................................................. 24

Serial Communications Peripherals..................................................................................................... 25

System Peripherals.............................................................................................................................. 26

Memory Peripherals............................................................................................................................. 27

Additional Features .............................................................................................................................. 27

Hardware Details ................................................................................................................................. 28

System Block Diagram ........................................................................................................................ 29

2.1

2.2

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.2.6

ARM Cortex-M3 Processor Core........................................................................................ 30

Block Diagram ..................................................................................................................................... 31

Functional Description ......................................................................................................................... 31

Serial Wire and JTAG Debug .............................................................................................................. 31

Embedded Trace Macrocell (ETM) ...................................................................................................... 32

Trace Port Interface Unit (TPIU) .......................................................................................................... 32

ROM Table .......................................................................................................................................... 32

Memory Protection Unit (MPU) ............................................................................................................ 32

Nested Vectored Interrupt Controller (NVIC) ....................................................................................... 32

5.1

5.2

5.2.1

5.2.2

5.2.3

5.2.4

5.3

5.4

5.4.1

5.4.2

Memory Map ........................................................................................................................ 33

Interrupts ............................................................................................................................. 35

JTAG Interface .................................................................................................................... 38

Block Diagram ..................................................................................................................................... 39

Functional Description ......................................................................................................................... 39

JTAG Interface Pins............................................................................................................................. 40

JTAG TAP Controller ........................................................................................................................... 41

Shift Registers ..................................................................................................................................... 42

Operational Considerations ................................................................................................................. 42

Initialization and Configuration............................................................................................................. 43

Register Descriptions........................................................................................................................... 44

Instruction Register (IR) ....................................................................................................................... 44

Data Registers ..................................................................................................................................... 46

6.1

6.1.1

System Control.................................................................................................................... 48

Functional Description ......................................................................................................................... 48

Device Identification............................................................................................................................. 48

October 6, 2006

Preliminary

Table of Contents

6.1.2

6.1.3

6.1.4

6.1.5

6.2

6.3

6.4

Reset Control ....................................................................................................................................... 48

Power Control ...................................................................................................................................... 51

Clock Control ....................................................................................................................................... 51

System Control .................................................................................................................................... 53

Initialization and Configuration............................................................................................................. 54

Register Map ....................................................................................................................................... 54

Register Descriptions........................................................................................................................... 55

7.1

7.2

7.2.1

7.2.2

7.3

7.3.1

7.3.2

7.4

7.5

Internal Memory .................................................................................................................. 86

Block Diagram ..................................................................................................................................... 86

Functional Description ......................................................................................................................... 86

SRAM Memory .................................................................................................................................... 86

Flash Memory ...................................................................................................................................... 87

Initialization and Configuration............................................................................................................. 88

Changing Flash Protection Bits ........................................................................................................... 88

Flash Programming ............................................................................................................................. 89

Register Map ....................................................................................................................................... 89

Register Descriptions........................................................................................................................... 90

8.1

8.2

8.2.1

8.2.2

8.2.3

8.2.4

8.2.5

8.2.6

8.3

8.4

8.5

General-Purpose Input/Outputs (GPIOs) ........................................................................ 100

Block Diagram ................................................................................................................................... 101

Functional Description ....................................................................................................................... 101

Data Register Operation .................................................................................................................... 102

Data Direction .................................................................................................................................... 103

Interrupt Operation............................................................................................................................. 103

Mode Control ..................................................................................................................................... 104

Pad Configuration .............................................................................................................................. 104

Identification....................................................................................................................................... 104

Initialization and Configuration........................................................................................................... 104

Register Map ..................................................................................................................................... 106

Register Descriptions......................................................................................................................... 107

9.1

9.2

9.2.1

9.2.2

9.2.3

9.3

9.3.1

9.3.2

9.3.3

9.3.4

9.3.5

9.3.6

9.4

9.5

General-Purpose Timers .................................................................................................. 138

Block Diagram ................................................................................................................................... 139

Functional Description ....................................................................................................................... 139

GPTM Reset Conditions .................................................................................................................... 139

32-Bit Timer Operating Modes........................................................................................................... 140

16-Bit Timer Operating Modes........................................................................................................... 141

Initialization and Configuration........................................................................................................... 145

32-Bit One-Shot/Periodic Timer Mode ............................................................................................... 145

32-Bit Real-Time Clock (RTC) Mode ................................................................................................. 146

16-Bit One-Shot/Periodic Timer Mode ............................................................................................... 146

16-Bit Input Edge Count Mode .......................................................................................................... 146

16-Bit Input Edge Timing Mode ......................................................................................................... 147

16-Bit PWM Mode.............................................................................................................................. 147

Register Map ..................................................................................................................................... 148

Register Descriptions......................................................................................................................... 149

10.

10.1

10.2

10.3

10.4

Watchdog Timer ................................................................................................................ 170

Block Diagram ................................................................................................................................... 170

Functional Description ....................................................................................................................... 171

Initialization and Configuration........................................................................................................... 171

Register Map ..................................................................................................................................... 171

Preliminary

October 6, 2006

LM3S102 Data Sheet

10.5

Register Descriptions......................................................................................................................... 172

11.

11.1

11.2

11.2.1

11.2.2

11.2.3

11.2.4

11.2.5

11.2.6

11.3

11.4

11.5

Universal Asynchronous Receiver/Transmitter (UART)................................................ 193

Block Diagram ................................................................................................................................... 194

Functional Description ....................................................................................................................... 194

Transmit/Receive Logic ..................................................................................................................... 194

Baud-Rate Generation ....................................................................................................................... 195

Data Transmission ............................................................................................................................. 196

FIFO Operation .................................................................................................................................. 196

Interrupts............................................................................................................................................ 196

Loopback Operation .......................................................................................................................... 197

Initialization and Configuration........................................................................................................... 197

Register Map ..................................................................................................................................... 198

Register Descriptions......................................................................................................................... 199

12.

12.1

12.2

12.2.1

12.2.2

12.2.3

12.2.4

12.3

12.4

12.5

Synchronous Serial Interface (SSI) ................................................................................. 229

Block Diagram ................................................................................................................................... 229

Functional Description ....................................................................................................................... 230

Bit Rate Generation ........................................................................................................................... 230

FIFO Operation .................................................................................................................................. 230

Interrupts............................................................................................................................................ 230

Frame Formats .................................................................................................................................. 231

Initialization and Configuration........................................................................................................... 238

Register Map ..................................................................................................................................... 239

Register Descriptions......................................................................................................................... 240

13.

13.1

13.2

13.2.1

13.2.2

13.3

13.4

13.5

13.6

Inter-Integrated Circuit (I2C) Interface ............................................................................ 264

Block Diagram ................................................................................................................................... 264

Functional Description ....................................................................................................................... 264

C Bus Functional Overview ............................................................................................................. 265

Available Speed Modes ..................................................................................................................... 272

Initialization and Configuration........................................................................................................... 273

Register Map ..................................................................................................................................... 273

Register Descriptions (I2C Master).................................................................................................... 274

Register Descriptions (I2C Slave)...................................................................................................... 288

14.

14.1

14.2

14.2.1

14.3

14.4

14.5

Analog Comparator........................................................................................................... 296

Block Diagram ................................................................................................................................... 296

Functional Description ....................................................................................................................... 296

Internal Reference Programming....................................................................................................... 297

Initialization and Configuration........................................................................................................... 298

Register Map ..................................................................................................................................... 299

Register Descriptions......................................................................................................................... 299

15.

16.

17.

18.

18.1

18.1.1

18.1.2

18.1.3

18.1.4

Pin Diagram ....................................................................................................................... 307

Signal Tables ..................................................................................................................... 308

Operating Characteristics ................................................................................................ 315

Electrical Characteristics ................................................................................................. 316

DC Characteristics ............................................................................................................................. 316

Maximum Ratings .............................................................................................................................. 316

Recommended DC Operating Conditions ......................................................................................... 316

On-Chip Low Drop-Out (LDO) Regulator Characteristics .................................................................. 317

Power Specifications ......................................................................................................................... 318

October 6, 2006

Preliminary

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