PR ELIMIN ARY
LM3S1627 Microcontroller
DATA SHE ET
DS-LM3S1627- 4 28 3
Copyrig ht
©
2007-2008 Luminary Micro, Inc.
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©
2007-2008 Luminary Micro, Inc. All rights reserved. Stellaris, Luminary Micro, and the Luminary Micro logo are registered trademarks of
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Preliminary
November 18, 2008
LM3S1627 Microcontroller
Table of Contents
Revision History ............................................................................................................................. 20
About This Document .................................................................................................................... 21
Audience ..............................................................................................................................................
About This Manual ................................................................................................................................
Related Documents ...............................................................................................................................
Documentation Conventions ..................................................................................................................
21
21
21
21
24
32
33
35
35
36
37
37
38
39
39
40
42
42
43
43
43
43
43
44
1
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
Architectural Overview ...................................................................................................... 24
Product Features ......................................................................................................................
Target Applications ....................................................................................................................
High-Level Block Diagram .........................................................................................................
Functional Overview ..................................................................................................................
ARM Cortex™-M3 .....................................................................................................................
Motor Control Peripherals ..........................................................................................................
Analog Peripherals ....................................................................................................................
Serial Communications Peripherals ............................................................................................
System Peripherals ...................................................................................................................
Memory Peripherals ..................................................................................................................
Additional Features ...................................................................................................................
Hardware Details ......................................................................................................................
Block Diagram ..........................................................................................................................
Functional Description ...............................................................................................................
Serial Wire and JTAG Debug .....................................................................................................
Embedded Trace Macrocell (ETM) .............................................................................................
Trace Port Interface Unit (TPIU) .................................................................................................
ROM Table ...............................................................................................................................
Memory Protection Unit (MPU) ...................................................................................................
Nested Vectored Interrupt Controller (NVIC) ................................................................................
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
ARM Cortex-M3 Processor Core ...................................................................................... 41
3
4
5
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.4
5.4.1
5.4.2
Memory Map ....................................................................................................................... 47
Interrupts ............................................................................................................................ 50
JTAG Interface .................................................................................................................... 53
Block Diagram ..........................................................................................................................
Functional Description ...............................................................................................................
JTAG Interface Pins ..................................................................................................................
JTAG TAP Controller .................................................................................................................
Shift Registers ..........................................................................................................................
Operational Considerations ........................................................................................................
Initialization and Configuration ...................................................................................................
Register Descriptions ................................................................................................................
Instruction Register (IR) .............................................................................................................
Data Registers ..........................................................................................................................
54
54
55
56
57
57
60
60
60
62
6
6.1
6.1.1
System Control ................................................................................................................... 65
Functional Description ............................................................................................................... 65
Device Identification .................................................................................................................. 65
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Table of Contents
6.1.2
6.1.3
6.1.4
6.1.5
6.1.6
6.2
6.3
6.4
Reset Control ............................................................................................................................
Non-Maskable Interrupt .............................................................................................................
Power Control ...........................................................................................................................
Clock Control ............................................................................................................................
System Control .........................................................................................................................
Initialization and Configuration ...................................................................................................
Register Map ............................................................................................................................
Register Descriptions ................................................................................................................
65
68
68
68
72
73
73
74
7
7.1
7.2
7.2.1
7.2.2
7.2.3
7.3
7.3.1
7.3.2
7.4
7.5
7.6
7.7
Internal Memory ............................................................................................................... 127
Block Diagram ........................................................................................................................ 127
Functional Description ............................................................................................................. 127
SRAM Memory ........................................................................................................................ 127
ROM Memory ......................................................................................................................... 128
Flash Memory ......................................................................................................................... 128
Flash Memory Initialization and Configuration ........................................................................... 129
Flash Programming ................................................................................................................. 129
Nonvolatile Register Programming ........................................................................................... 130
Register Map .......................................................................................................................... 131
ROM Register Descriptions (System Control Offset) .................................................................. 132
Flash Register Descriptions (Flash Control Offset) ..................................................................... 133
Flash Register Descriptions (System Control Offset) .................................................................. 140
8
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
8.2.10
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.4
8.5
8.6
Micro Direct Memory Access (μDMA) ............................................................................ 156
Block Diagram ........................................................................................................................ 157
Functional Description ............................................................................................................. 157
Channel Assigments ................................................................................................................ 158
Priority .................................................................................................................................... 158
Arbitration Size ........................................................................................................................ 158
Request Types ........................................................................................................................ 158
Channel Configuration ............................................................................................................. 159
Transfer Modes ....................................................................................................................... 161
Transfer Size and Increment .................................................................................................... 169
Peripheral Interface ................................................................................................................. 169
Software Request .................................................................................................................... 169
Interrupts and Errors ................................................................................................................ 170
Initialization and Configuration ................................................................................................. 170
Module Initialization ................................................................................................................. 170
Configuring a Memory-to-Memory Transfer ............................................................................... 170
Configuring a Peripheral for Simple Transmit ............................................................................ 172
Configuring a Peripheral for Ping-Pong Receive ........................................................................ 173
Register Map .......................................................................................................................... 176
μDMA Channel Control Structure ............................................................................................. 177
μDMA Register Descriptions .................................................................................................... 183
9
9.1
9.1.1
9.1.2
9.1.3
9.1.4
General-Purpose Input/Outputs (GPIOs) ....................................................................... 217
Functional Description .............................................................................................................
Data Control ...........................................................................................................................
Interrupt Control ......................................................................................................................
Mode Control ..........................................................................................................................
Commit Control .......................................................................................................................
217
219
220
221
221
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LM3S1627 Microcontroller
9.1.5
9.1.6
9.2
9.3
9.4
Pad Control ............................................................................................................................. 221
Identification ........................................................................................................................... 222
Initialization and Configuration ................................................................................................. 222
Register Map .......................................................................................................................... 223
Register Descriptions .............................................................................................................. 225
10
10.1
10.2
10.2.1
10.2.2
10.2.3
10.3
10.3.1
10.3.2
10.3.3
10.3.4
10.3.5
10.3.6
10.4
10.5
General-Purpose Timers ................................................................................................. 262
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
GPTM Reset Conditions ..........................................................................................................
32-Bit Timer Operating Modes ..................................................................................................
16-Bit Timer Operating Modes ..................................................................................................
Initialization and Configuration .................................................................................................
32-Bit One-Shot/Periodic Timer Mode .......................................................................................
32-Bit Real-Time Clock (RTC) Mode .........................................................................................
16-Bit One-Shot/Periodic Timer Mode .......................................................................................
16-Bit Input Edge Count Mode .................................................................................................
16-Bit Input Edge Timing Mode ................................................................................................
16-Bit PWM Mode ...................................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
263
264
264
264
265
269
269
270
270
271
271
272
272
273
297
297
298
298
299
11
11.1
11.2
11.3
11.4
11.5
Watchdog Timer ............................................................................................................... 296
12
12.1
12.2
12.2.1
12.2.2
12.2.3
12.2.4
12.2.5
12.2.6
12.3
12.3.1
12.3.2
12.4
12.5
Analog-to-Digital Converter (ADC) ................................................................................. 320
Block Diagram ........................................................................................................................ 320
Functional Description ............................................................................................................. 321
Sample Sequencers ................................................................................................................ 321
Module Control ........................................................................................................................ 322
Hardware Sample Averaging Circuit ......................................................................................... 323
Analog-to-Digital Converter ...................................................................................................... 323
Differential Sampling ............................................................................................................... 323
Internal Temperature Sensor .................................................................................................... 325
Initialization and Configuration ................................................................................................. 326
Module Initialization ................................................................................................................. 326
Sample Sequencer Configuration ............................................................................................. 326
Register Map .......................................................................................................................... 327
Register Descriptions .............................................................................................................. 328
13
13.1
13.2
13.2.1
13.2.2
13.2.3
13.2.4
Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 355
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Transmit/Receive Logic ...........................................................................................................
Baud-Rate Generation .............................................................................................................
Data Transmission ..................................................................................................................
Serial IR (SIR) .........................................................................................................................
356
356
356
357
358
358
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