PR ELIMIN ARY
LM3S6432 Microcontroller
DATA SHE ET
DS-LM3S6432- 4 28 3
Copyrig ht
©
2007-2008 Luminary Micro, Inc.
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©
2007-2008 Luminary Micro, Inc. All rights reserved. Stellaris, Luminary Micro, and the Luminary Micro logo are registered trademarks of
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Preliminary
November 16, 2008
LM3S6432 Microcontroller
Table of Contents
Revision History ............................................................................................................................. 18
About This Document .................................................................................................................... 20
Audience ..............................................................................................................................................
About This Manual ................................................................................................................................
Related Documents ...............................................................................................................................
Documentation Conventions ..................................................................................................................
20
20
20
20
23
31
32
34
34
34
35
36
37
38
38
39
41
41
41
42
42
42
42
42
1
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
Architectural Overview ...................................................................................................... 23
Product Features ......................................................................................................................
Target Applications ....................................................................................................................
High-Level Block Diagram .........................................................................................................
Functional Overview ..................................................................................................................
ARM Cortex™-M3 .....................................................................................................................
Motor Control Peripherals ..........................................................................................................
Analog Peripherals ....................................................................................................................
Serial Communications Peripherals ............................................................................................
System Peripherals ...................................................................................................................
Memory Peripherals ..................................................................................................................
Additional Features ...................................................................................................................
Hardware Details ......................................................................................................................
Block Diagram ..........................................................................................................................
Functional Description ...............................................................................................................
Serial Wire and JTAG Debug .....................................................................................................
Embedded Trace Macrocell (ETM) .............................................................................................
Trace Port Interface Unit (TPIU) .................................................................................................
ROM Table ...............................................................................................................................
Memory Protection Unit (MPU) ...................................................................................................
Nested Vectored Interrupt Controller (NVIC) ................................................................................
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
ARM Cortex-M3 Processor Core ...................................................................................... 40
3
4
5
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.4
5.4.1
5.4.2
Memory Map ....................................................................................................................... 46
Interrupts ............................................................................................................................ 48
JTAG Interface .................................................................................................................... 51
Block Diagram ..........................................................................................................................
Functional Description ...............................................................................................................
JTAG Interface Pins ..................................................................................................................
JTAG TAP Controller .................................................................................................................
Shift Registers ..........................................................................................................................
Operational Considerations ........................................................................................................
Initialization and Configuration ...................................................................................................
Register Descriptions ................................................................................................................
Instruction Register (IR) .............................................................................................................
Data Registers ..........................................................................................................................
52
52
52
54
55
55
58
58
58
60
6
6.1
6.1.1
System Control ................................................................................................................... 63
Functional Description ............................................................................................................... 63
Device Identification .................................................................................................................. 63
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Table of Contents
6.1.2
6.1.3
6.1.4
6.1.5
6.2
6.3
6.4
Reset Control ............................................................................................................................
Power Control ...........................................................................................................................
Clock Control ............................................................................................................................
System Control .........................................................................................................................
Initialization and Configuration ...................................................................................................
Register Map ............................................................................................................................
Register Descriptions ................................................................................................................
63
66
67
70
71
72
73
7
7.1
7.2
7.2.1
7.2.2
7.3
7.3.1
7.3.2
7.4
7.5
7.6
Internal Memory ............................................................................................................... 125
Block Diagram ........................................................................................................................ 125
Functional Description ............................................................................................................. 125
SRAM Memory ........................................................................................................................ 125
Flash Memory ......................................................................................................................... 126
Flash Memory Initialization and Configuration ........................................................................... 127
Flash Programming ................................................................................................................. 127
Nonvolatile Register Programming ........................................................................................... 127
Register Map .......................................................................................................................... 128
Flash Register Descriptions (Flash Control Offset) ..................................................................... 129
Flash Register Descriptions (System Control Offset) .................................................................. 136
8
8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.2
8.3
8.4
General-Purpose Input/Outputs (GPIOs) ....................................................................... 149
Functional Description ............................................................................................................. 149
Data Control ........................................................................................................................... 150
Interrupt Control ...................................................................................................................... 151
Mode Control .......................................................................................................................... 152
Commit Control ....................................................................................................................... 152
Pad Control ............................................................................................................................. 152
Identification ........................................................................................................................... 153
Initialization and Configuration ................................................................................................. 153
Register Map .......................................................................................................................... 154
Register Descriptions .............................................................................................................. 156
9
9.1
9.2
9.2.1
9.2.2
9.2.3
9.3
9.3.1
9.3.2
9.3.3
9.3.4
9.3.5
9.3.6
9.4
9.5
General-Purpose Timers ................................................................................................. 191
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
GPTM Reset Conditions ..........................................................................................................
32-Bit Timer Operating Modes ..................................................................................................
16-Bit Timer Operating Modes ..................................................................................................
Initialization and Configuration .................................................................................................
32-Bit One-Shot/Periodic Timer Mode .......................................................................................
32-Bit Real-Time Clock (RTC) Mode .........................................................................................
16-Bit One-Shot/Periodic Timer Mode .......................................................................................
16-Bit Input Edge Count Mode .................................................................................................
16-Bit Input Edge Timing Mode ................................................................................................
16-Bit PWM Mode ...................................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
192
192
193
193
194
198
198
199
199
200
200
201
201
202
10
10.1
10.2
Watchdog Timer ............................................................................................................... 227
Block Diagram ........................................................................................................................ 228
Functional Description ............................................................................................................. 228
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LM3S6432 Microcontroller
10.3
10.4
10.5
Initialization and Configuration ................................................................................................. 229
Register Map .......................................................................................................................... 229
Register Descriptions .............................................................................................................. 230
11
11.1
11.2
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.2.6
11.2.7
11.3
11.3.1
11.3.2
11.4
11.5
Analog-to-Digital Converter (ADC) ................................................................................. 251
Block Diagram ........................................................................................................................ 251
Functional Description ............................................................................................................. 252
Sample Sequencers ................................................................................................................ 252
Module Control ........................................................................................................................ 253
Hardware Sample Averaging Circuit ......................................................................................... 254
Analog-to-Digital Converter ...................................................................................................... 254
Differential Sampling ............................................................................................................... 254
Test Modes ............................................................................................................................. 256
Internal Temperature Sensor .................................................................................................... 257
Initialization and Configuration ................................................................................................. 257
Module Initialization ................................................................................................................. 257
Sample Sequencer Configuration ............................................................................................. 258
Register Map .......................................................................................................................... 258
Register Descriptions .............................................................................................................. 259
12
12.1
12.2
12.2.1
12.2.2
12.2.3
12.2.4
12.2.5
12.2.6
12.2.7
12.2.8
12.3
12.4
12.5
Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 287
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Transmit/Receive Logic ...........................................................................................................
Baud-Rate Generation .............................................................................................................
Data Transmission ..................................................................................................................
Serial IR (SIR) .........................................................................................................................
FIFO Operation .......................................................................................................................
Interrupts ................................................................................................................................
Loopback Operation ................................................................................................................
IrDA SIR block ........................................................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Bit Rate Generation .................................................................................................................
FIFO Operation .......................................................................................................................
Interrupts ................................................................................................................................
Frame Formats .......................................................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
I
2
C Bus Functional Overview ....................................................................................................
Available Speed Modes ...........................................................................................................
288
288
288
289
290
290
291
291
292
292
292
293
294
328
328
329
329
329
330
337
338
339
366
366
366
368
13
13.1
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.3
13.4
13.5
Synchronous Serial Interface (SSI) ................................................................................ 328
14
14.1
14.2
14.2.1
14.2.2
Inter-Integrated Circuit (I
2
C) Interface ............................................................................ 365
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