PR ELIMIN ARY
LM3S8933 Microcontroller
DATA SHE ET
DS-LM3S8933- 4 28 3
Copyrig ht
©
2007-2008 Luminary Micro, Inc.
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©
2007-2008 Luminary Micro, Inc. All rights reserved. Stellaris, Luminary Micro, and the Luminary Micro logo are registered trademarks of
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Preliminary
November 16, 2008
LM3S8933 Microcontroller
Table of Contents
Revision History ............................................................................................................................. 20
About This Document .................................................................................................................... 22
Audience ..............................................................................................................................................
About This Manual ................................................................................................................................
Related Documents ...............................................................................................................................
Documentation Conventions ..................................................................................................................
22
22
22
22
25
33
33
35
35
35
36
37
38
39
40
40
43
43
43
44
44
44
44
44
1
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
Architectural Overview ...................................................................................................... 25
Product Features ......................................................................................................................
Target Applications ....................................................................................................................
High-Level Block Diagram .........................................................................................................
Functional Overview ..................................................................................................................
ARM Cortex™-M3 .....................................................................................................................
Motor Control Peripherals ..........................................................................................................
Analog Peripherals ....................................................................................................................
Serial Communications Peripherals ............................................................................................
System Peripherals ...................................................................................................................
Memory Peripherals ..................................................................................................................
Additional Features ...................................................................................................................
Hardware Details ......................................................................................................................
Block Diagram ..........................................................................................................................
Functional Description ...............................................................................................................
Serial Wire and JTAG Debug .....................................................................................................
Embedded Trace Macrocell (ETM) .............................................................................................
Trace Port Interface Unit (TPIU) .................................................................................................
ROM Table ...............................................................................................................................
Memory Protection Unit (MPU) ...................................................................................................
Nested Vectored Interrupt Controller (NVIC) ................................................................................
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
ARM Cortex-M3 Processor Core ...................................................................................... 42
3
4
5
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.3
5.4
5.4.1
5.4.2
Memory Map ....................................................................................................................... 48
Interrupts ............................................................................................................................ 50
JTAG Interface .................................................................................................................... 53
Block Diagram ..........................................................................................................................
Functional Description ...............................................................................................................
JTAG Interface Pins ..................................................................................................................
JTAG TAP Controller .................................................................................................................
Shift Registers ..........................................................................................................................
Operational Considerations ........................................................................................................
Initialization and Configuration ...................................................................................................
Register Descriptions ................................................................................................................
Instruction Register (IR) .............................................................................................................
Data Registers ..........................................................................................................................
54
54
54
56
57
57
60
60
60
62
6
6.1
6.1.1
System Control ................................................................................................................... 65
Functional Description ............................................................................................................... 65
Device Identification .................................................................................................................. 65
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Table of Contents
6.1.2
6.1.3
6.1.4
6.1.5
6.2
6.3
6.4
Reset Control ............................................................................................................................
Power Control ...........................................................................................................................
Clock Control ............................................................................................................................
System Control .........................................................................................................................
Initialization and Configuration ...................................................................................................
Register Map ............................................................................................................................
Register Descriptions ................................................................................................................
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Register Access Timing ...........................................................................................................
Clock Source ..........................................................................................................................
Battery Management ...............................................................................................................
Real-Time Clock ......................................................................................................................
Non-Volatile Memory ...............................................................................................................
Power Control .........................................................................................................................
Initiating Hibernate ..................................................................................................................
Interrupts and Status ...............................................................................................................
Initialization and Configuration .................................................................................................
Initialization .............................................................................................................................
RTC Match Functionality (No Hibernation) ................................................................................
RTC Match/Wake-Up from Hibernation .....................................................................................
External Wake-Up from Hibernation ..........................................................................................
RTC/External Wake-Up from Hibernation ..................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
65
68
69
72
73
74
75
7
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.4
7.5
Hibernation Module .......................................................................................................... 129
130
130
130
131
132
132
133
133
133
134
134
134
134
135
135
135
135
136
8
8.1
8.2
8.2.1
8.2.2
8.3
8.3.1
8.3.2
8.4
8.5
8.6
Internal Memory ............................................................................................................... 149
Block Diagram ........................................................................................................................ 149
Functional Description ............................................................................................................. 149
SRAM Memory ........................................................................................................................ 149
Flash Memory ......................................................................................................................... 150
Flash Memory Initialization and Configuration ........................................................................... 151
Flash Programming ................................................................................................................. 151
Nonvolatile Register Programming ........................................................................................... 151
Register Map .......................................................................................................................... 152
Flash Register Descriptions (Flash Control Offset) ..................................................................... 153
Flash Register Descriptions (System Control Offset) .................................................................. 160
9
9.1
9.1.1
9.1.2
9.1.3
9.1.4
9.1.5
9.1.6
9.2
9.3
9.4
General-Purpose Input/Outputs (GPIOs) ....................................................................... 173
Functional Description ............................................................................................................. 173
Data Control ........................................................................................................................... 174
Interrupt Control ...................................................................................................................... 175
Mode Control .......................................................................................................................... 176
Commit Control ....................................................................................................................... 176
Pad Control ............................................................................................................................. 176
Identification ........................................................................................................................... 177
Initialization and Configuration ................................................................................................. 177
Register Map .......................................................................................................................... 178
Register Descriptions .............................................................................................................. 180
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Preliminary
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LM3S8933 Microcontroller
10
10.1
10.2
10.2.1
10.2.2
10.2.3
10.3
10.3.1
10.3.2
10.3.3
10.3.4
10.3.5
10.3.6
10.4
10.5
General-Purpose Timers ................................................................................................. 215
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
GPTM Reset Conditions ..........................................................................................................
32-Bit Timer Operating Modes ..................................................................................................
16-Bit Timer Operating Modes ..................................................................................................
Initialization and Configuration .................................................................................................
32-Bit One-Shot/Periodic Timer Mode .......................................................................................
32-Bit Real-Time Clock (RTC) Mode .........................................................................................
16-Bit One-Shot/Periodic Timer Mode .......................................................................................
16-Bit Input Edge Count Mode .................................................................................................
16-Bit Input Edge Timing Mode ................................................................................................
16-Bit PWM Mode ...................................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Initialization and Configuration .................................................................................................
Register Map ..........................................................................................................................
Register Descriptions ..............................................................................................................
216
217
217
217
218
222
222
223
223
224
224
225
225
226
252
252
253
253
254
11
11.1
11.2
11.3
11.4
11.5
Watchdog Timer ............................................................................................................... 251
12
12.1
12.2
12.2.1
12.2.2
12.2.3
12.2.4
12.2.5
12.2.6
12.2.7
12.3
12.3.1
12.3.2
12.4
12.5
Analog-to-Digital Converter (ADC) ................................................................................. 275
Block Diagram ........................................................................................................................ 275
Functional Description ............................................................................................................. 276
Sample Sequencers ................................................................................................................ 276
Module Control ........................................................................................................................ 277
Hardware Sample Averaging Circuit ......................................................................................... 278
Analog-to-Digital Converter ...................................................................................................... 278
Differential Sampling ............................................................................................................... 278
Test Modes ............................................................................................................................. 280
Internal Temperature Sensor .................................................................................................... 281
Initialization and Configuration ................................................................................................. 281
Module Initialization ................................................................................................................. 281
Sample Sequencer Configuration ............................................................................................. 282
Register Map .......................................................................................................................... 282
Register Descriptions .............................................................................................................. 283
13
13.1
13.2
13.2.1
13.2.2
13.2.3
13.2.4
13.2.5
13.2.6
13.2.7
13.2.8
13.3
Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 311
Block Diagram ........................................................................................................................
Functional Description .............................................................................................................
Transmit/Receive Logic ...........................................................................................................
Baud-Rate Generation .............................................................................................................
Data Transmission ..................................................................................................................
Serial IR (SIR) .........................................................................................................................
FIFO Operation .......................................................................................................................
Interrupts ................................................................................................................................
Loopback Operation ................................................................................................................
IrDA SIR block ........................................................................................................................
Initialization and Configuration .................................................................................................
312
312
312
313
314
314
315
315
316
316
316
November 16, 2008
Preliminary
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