DF
N2
020
-6
PBSS4160PANP
14 January 2013
60 V, 1 A NPN/PNP low VCEsat (BISS) transistor
Product data sheet
1. General description
NPN/PNP low V
CEsat
Breakthrough In Small Signal (BISS) transistor in a leadless
medium power DFN2020-6 (SOT1118) Surface-Mounted Device (SMD) plastic package.
NPN/NPN complement: PBSS4160PAN. PNP/PNP complement: PBSS5160PAP.
2. Features and benefits
•
•
•
•
•
•
Very low collector-emitter saturation voltage V
CEsat
High collector current capability I
C
and I
CM
High collector current gain h
FE
at high I
C
Reduced Printed-Circuit Board (PCB) requirements
High efficiency due to less heat generation
AEC-Q101 qualified
3. Applications
•
•
•
•
•
Load switch
Battery-driven devices
Power management
Charging circuits
Power switches (e.g. motors, fans)
4. Quick reference data
Table 1.
Symbol
V
CEO
I
C
I
CM
TR1 (NPN)
R
CEsat
collector-emitter
saturation resistance
I
C
= 0.5 A; I
B
= 50 mA; pulsed;
t
p
≤ 300 µs; δ ≤ 0.02 ; T
amb
= 25 °C
-
-
240
mΩ
Quick reference data
Parameter
collector-emitter
voltage
collector current
peak collector current
single pulse; t
p
≤ 1 ms
Conditions
open base
Min
-
-
-
Typ
-
-
-
Max
60
1
1.5
Unit
V
A
A
Per transistor; for the PNP transistor with negative polarity
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NXP Semiconductors
PBSS4160PANP
60 V, 1 A NPN/PNP low VCEsat (BISS) transistor
Symbol
TR2 (PNP)
R
CEsat
Parameter
collector-emitter
saturation resistance
Conditions
I
C
= -0.5 A; I
B
= -50 mA; pulsed;
t
p
≤ 300 µs; δ ≤ 0.02 ; T
amb
= 25 °C
Min
-
Typ
-
Max
360
Unit
mΩ
5. Pinning information
Table 2.
Pin
1
2
3
4
5
6
7
8
Pinning information
Symbol Description
E1
B1
C2
E2
B2
C1
C1
C2
emitter TR1
base TR1
collector TR2
emitter TR2
base TR2
collector TR1
collector TR1
collector TR2
1
2
3
7
8
TR1
TR2
Simplified outline
6
5
4
Graphic symbol
C1
B2
E2
E1
B1
sym139
C2
Transparent top view
DFN2020-6 (SOT1118)
6. Ordering information
Table 3.
Ordering information
Package
Name
PBSS4160PANP
DFN2020-6
Description
plastic thermal enhanced ultra thin small outline package; no
leads; 6 terminals; body 2 x 2 x 0.65 mm
Version
SOT1118
Type number
7. Marking
Table 4.
Marking codes
Marking code
2M
Type number
PBSS4160PANP
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
CBO
V
CEO
PBSS4160PANP
Parameter
collector-base voltage
collector-emitter voltage
Conditions
open emitter
open base
All information provided in this document is subject to legal disclaimers.
Min
-
-
Max
60
60
Unit
V
V
2 / 21
Per transistor; for the PNP transistor with negative polarity
© NXP B.V. 2013. All rights reserved
Product data sheet
14 January 2013
NXP Semiconductors
PBSS4160PANP
60 V, 1 A NPN/PNP low VCEsat (BISS) transistor
Symbol
V
EBO
I
C
I
CM
I
B
I
BM
P
tot
Parameter
emitter-base voltage
collector current
peak collector current
base current
peak base current
total power dissipation
Conditions
open collector
Min
-
-
Max
7
1
1.5
0.3
1
370
570
530
700
450
760
700
1450
510
780
730
960
620
1040
960
2000
150
150
150
Unit
V
A
A
A
A
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
°C
°C
°C
single pulse; t
p
≤ 1 ms
-
-
single pulse; t
p
≤ 1 ms
T
amb
≤ 25 °C
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-55
-65
Per device
P
tot
total power dissipation
T
amb
≤ 25 °C
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
T
j
T
amb
T
stg
junction temperature
ambient temperature
storage temperature
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
Device mounted on an FR4 PCB, single-sided 35 µm copper strip line, tin-plated and standard footprint.
Device mounted on an FR4 PCB, single-sided 35 µm copper strip line, tin-plated, mounting pad for
collector 1 cm .
Device mounted on 4-layer PCB 35 µm copper strip line, tin-plated and standard footprint.
2
Device mounted on 4-layer PCB 35 µm copper strip line, tin-plated, mounting pad for collector 1 cm .
Device mounted on an FR4 PCB, single-sided 70 µm copper strip line, tin-plated and standard footprint.
Device mounted on an FR4 PCB, single-sided 70 µm copper strip line, tin-plated, mounting pad for
collector 1 cm .
Device mounted on 4-layer PCB 70 µm copper strip line, tin-plated and standard footprint.
2
2
Device mounted on 4-layer PCB 70 µm copper strip line, tin-plated, mounting pad for collector 1 cm .
2
PBSS4160PANP
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved
Product data sheet
14 January 2013
3 / 21
NXP Semiconductors
PBSS4160PANP
60 V, 1 A NPN/PNP low VCEsat (BISS) transistor
1.5
P
tot
(W)
1.0
006aad165
(1)
(2)
(3) (4)
(5)
(6)
(7)
(8)
0.5
0
-75
-25
25
75
2
125
175
T
amb
(°C)
(1) 4-layer PCB 70 µm, mounting pad for collector 1 cm
(2) FR4 PCB 70 µm, mounting pad for collector 1 cm
(3) 4-layer PCB 70 µm, standard footprint
(5) FR4 PCB 35 µm, mounting pad for collector 1 cm
(6) 4-layer PCB 35 µm, standard footprint
(7) FR4 PCB 70 µm, standard footprint
(8) FR4 PCB 35 µm, standard footprint
Fig. 1.
Per transistor: power derating curves
2
(4) 4-layer PCB 35 µm, mounting pad for collector 1 cm
2
2
9. Thermal characteristics
Table 6.
Symbol
Per transistor
R
th(j-a)
thermal resistance
from junction to
ambient
in free air
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
Thermal characteristics
Parameter
Conditions
Min
-
-
-
-
-
-
-
-
-
Typ
-
-
-
-
-
-
-
-
-
Max
338
219
236
179
278
164
179
86
30
Unit
K/W
K/W
K/W
K/W
K/W
K/W
K/W
K/W
K/W
R
th(j-sp)
thermal resistance
from junction to solder
point
PBSS4160PANP
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved
Product data sheet
14 January 2013
4 / 21
NXP Semiconductors
PBSS4160PANP
60 V, 1 A NPN/PNP low VCEsat (BISS) transistor
Symbol
Per device
R
th(j-a)
Parameter
thermal resistance
from junction to
ambient
Conditions
in free air
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
Min
-
-
-
-
-
-
-
-
Typ
-
-
-
-
-
-
-
-
Max
245
160
171
130
202
120
130
63
Unit
K/W
K/W
K/W
K/W
K/W
K/W
K/W
K/W
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
10
3
Z
th(j-a)
(K/W)
10
2
duty cycle = 1
0.75
0.33
0.1
0.05
10
0.02
0.01
0.5
0.2
Device mounted on an FR4 PCB, single-sided 35 µm copper strip line, tin-plated and standard footprint.
Device mounted on an FR4 PCB, single-sided 35 µm copper strip line, tin-plated, mounting pad for
collector 1 cm .
Device mounted on 4-layer PCB 35 µm copper strip line, tin-plated and standard footprint.
2
Device mounted on 4-layer PCB 35 µm copper strip line, tin-plated, mounting pad for collector 1 cm .
Device mounted on an FR4 PCB, single-sided 70 µm copper strip line, tin-plated and standard footprint.
Device mounted on an FR4 PCB, single-sided 70 µm copper strip line, tin-plated, mounting pad for
collector 1 cm .
Device mounted on 4-layer PCB 70 µm copper strip line, tin-plated and standard footprint.
2
2
Device mounted on 4-layer PCB 70 µm copper strip line, tin-plated, mounting pad for collector 1 cm .
006aad166
2
0
1
10
-5
10
-4
10
-3
10
-2
10
-1
1
10
10
2
t
p
(s)
10
3
FR4 PCB 35 µm, standard footprint
Fig. 2.
Per transistor: transient thermal impedance from junction to ambient as a function of pulse duration;
typical values
PBSS4160PANP
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved
Product data sheet
14 January 2013
5 / 21
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