INTEGRATED CIRCUITS
PCA9515A
I
2
C-bus repeater
Objective data sheet
2004 Jun 17
Philips
Semiconductors
Philips Semiconductors
Objective data sheet
I
2
C-bus repeater
PCA9515A
DESCRIPTION
The PCA9515A is a CMOS integrated circuit intended for application
in I
2
C and SMBus systems.
While retaining all the operating modes and features of the I
2
C
system it permits extension of the I
2
C-bus by buffering both the data
(SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF.
The I
2
C-bus capacitance limit of 400 pF restricts the number of
devices and bus length. Using the PCA9515A enables the system
designer to isolate two halves of a bus, thus more devices or longer
length can be accommodated. It can also be used to run two buses,
one at 5 V and the other at 3.3 V or a 400 kHz and 100 kHz bus,
where the 100 kHz bus is isolated when 400 kHz operation of the
other is required.
Two or more PCA9515As cannot be put in series.
The PCA9515A
design does not allow this configuration. Since there is no direction
pin, slightly different “legal” low voltage levels are used to avoid
lock-up conditions between the input and the output. A “regular
LOW” applied at the input of a PCA9515A will be propagated as a
“buffered LOW” with a slightly higher value. When this “buffered
LOW” is applied to another PCA9515A, PCA9516A, or PCA9518 in
series, the second PCA9515A, PCA9516A, or PCA9518 will not
recognize it as a “regular LOW” and will not propagate it as a
“buffered LOW” again. The PCA9510/9511/9513/9514 and
PCA9512 cannot be used in series with the PCA9515A, PCA9516A,
or PCA9518 but can be used in series with themselves since they
use shifting instead of static offsets to avoid lock-up conditions.
PIN CONFIGURATION
n.c. 1
SCL0
SDA0
GND
2
3
4
8
7
6
5
V
CC
SCL1
SDA1
EN
SU01322
Figure 1. Pin configuration
PIN DESCRIPTION
PIN
1
2
3
4
5
6
7
8
SYMBOL
n.c.
SCL0
SDA0
GND
EN
SDA1
SCL1
V
CC
FUNCTION
No connection
Serial clock bus 0
Serial data bus 0
Supply ground
Active-HIGH repeater enable input
Serial data bus 1
Serial clock bus 1
Supply power
FEATURES
•
2 channel, bi-directional buffer
•
I
2
C-bus and SMBus compatible
•
Active-HIGH repeater enable input
•
Open-drain input/outputs
•
Lock-up free operation
•
Supports arbitration and clock stretching across the repeater
•
Accommodates standard mode and fast mode I
2
C devices and
•
Powered-off high-impedance I
2
C pins
•
Operating supply voltage range of 2.3 V to 3.6 V
•
5.5 V tolerant I
2
C and enable pins
•
0 to 400 kHz clock frequency
1
•
ESD protection exceeds 2000 V HBM per JESD22-A114,
•
Latch-up testing is done to JEDEC Standard JESD78 which
•
Package offerings: SO and TSSOP
ORDERING INFORMATION
PACKAGES
8-pin plastic SO
8-pin plastic TSSOP
TEMPERATURE RANGE
–40
°C
to +85
°C
–40
°C
to +85
°C
exceeds 100 mA.
200 V MM per JESD22-A115, and 1000 V CDM per
JESD22-C101.
multiple masters
ORDER CODE
PCA9515AD
PCA9515ADP
TOPSIDE MARK
PA9515A
9515A
DRAWING NUMBER
SOT96-1
SOT505-1
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
1.
The maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater.
2004 Jun 17
2
Philips Semiconductors
Objective data sheet
I
2
C-bus repeater
PCA9515A
V
CC
PCA9515A
SDA0
SDA1
SCL0
SCL1
PULL-UP
RESISTOR
EN
SW02244
GND
Figure 2. PCA9515A block diagram
The output pull-down of each internal buffer is set for approximately
0.5 V, while the input threshold of each internal buffer is set about
0.07 V lower, when the output is internally driven LOW. This
prevents a lock-up condition from occurring.
I
2
C Systems
As with the standard I
2
C system, pull-up resistors are required to
provide the logic HIGH levels on the Buffered bus. (Standard
open-collector configuration of the I
2
C-bus). The size of these
pull-up resistors depends on the system, but each side of the
repeater must have a pull-up resistor. This part designed to work
with standard mode and fast mode I
2
C devices in addition to SMBus
devices. Standard mode I
2
C devices only specify 3 mA output drive,
this limits the termination current to 3 mA in a generic I
2
C system
where standard mode devices and multiple masters are possible.
Under certain conditions higher termination currents can be used.
Please see Application Note AN255
“I
2
C & SMBus Repeaters, Hubs
and Expanders”
for additional information on sizing resistors and
precautions when using more than one PCA9515A/PCA9516A in a
system or using the PCA9515A/16A in conjunction with the P82B96.
FUNCTIONAL DESCRIPTION
The PCA9515A integrated circuit contains two identical buffer
circuits which enable I
2
C and similar bus systems to be extended
without degradation of system performance.
The PCA9515A contains two bi-directional, open drain buffers
specifically designed to support the standard LOW-level-contention
arbitration of the I
2
C-bus. Except during arbitration or clock
stretching, the PCA9515A acts like a pair of non-inverting, open
drain buffers, one for SDA and one for SCL.
Enable
The EN pin is active HIGH with an internal pull up and allows the
user to select when the repeater is active. This can be used to
isolate a badly behaved slave on power up until after the system
power up reset. It should never change state during an I
2
C
operation because disabling during a bus operation will hang the
bus and enabling part way through a bus cycle could confuse the
I
2
C parts being enabled.
The enable pin should only change state when the global bus and
the repeater port are in an idle state to prevent system failures.
2004 Jun 17
3
Philips Semiconductors
Objective data sheet
I
2
C-bus repeater
PCA9515A
APPLICATION INFORMATION
A typical application is shown in Figure 3. In this example, the
system master is running on a 3.3 V I
2
C-bus while the slave is
connected to a 5 V bus. Both buses run at 100 kHz unless the slave
bus is isolated and then the master bus can run at 400 kHz. Master
devices can be placed on either bus.
3.3 V
5V
The PCA9515A is 5 V tolerant so it does not require any additional
circuitry to translate between the different bus voltages.
When one side of the PCA9515A is pulled LOW by a device on the
I
2
C-bus, a CMOS hysteresis type input detects the falling edge and
causes an internal driver on the other side to turn on, thus causing
the other side to also go LOW. The side driven LOW by the
PCA9515A will typically be at V
OL
= 0.5 V.
In order to illustrate what would be seen in a typical application, refer
to Figures 4 and 5. If the bus master in Figure 3 were to write to the
slave through the PCA9515A, we would see the waveform shown in
Figure 4 on Bus 0. This looks like a normal I
2
C transmission until the
falling edge of the 8
th
clock pulse. At that point, the master releases
the data line (SDA) while the slave pulls it LOW through the
PCA9515A. Because the V
OL
of the PCA9515A is typically around
0.5 V, a step in the SDA will be seen. After the master has
transmitted the 9
th
clock pulse, the slave releases the data line.
SDA
SCL
BUS
MASTER
400 kHz
SDA0
SCL0
SDA1
SCL1
SDA
SCL
SLAVE
100 kHz
PCA9515A
EN
BUS0
BUS1
SW02245
Figure 3. Typical application
2 V/DIV
9th CLOCK PULSE
V
OL
OF PCA9515A
V
OL
OF MASTER
SW02247
Figure 4. Bus 0 waveform
2004 Jun 17
4
Philips Semiconductors
Objective data sheet
I
2
C-bus repeater
PCA9515A
On the Bus 1 side of the PCA9515A, the clock and data lines would
have a positive offset from ground equal to the V
OL
of the
PCA9515A. After the 8
th
clock pulse, the data line will be pulled to
the V
OL
of the slave device that is very close to ground in our
example.
It is important to note that any arbitration or clock stretching events
on Bus 1 require that the V
OL
of the devices on Bus 1 be 70 mV
below the V
OL
of the PCA9515A (see V
OL
– V
ilc
in the DC
Characteristics section) to be recognized by the PCA9515A and
then transmitted to Bus 0.
9th CLOCK PULSE
2 V/DIV
V
OL
OF PCA9515A
V
OL
OF SLAVE
SW02246
Figure 5. Bus 1 waveform
2004 Jun 17
5
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