24AA256/24LC256/24FC256
256K I
2
C
™
CMOS Serial EEPROM
Device Selection Table
Part
Number
24AA256
24LC256
24FC256
Note 1:
2:
V
CC
Range
1.7-5.5V
2.5-5.5V
1.7-5.5V
Max. Clock
Frequency
400 kHz
(1)
400 kHz
1 MHz
(2)
Temp.
Ranges
I
I, E
I
• Temperature Ranges:
- Industrial (I):
- Automotive (E):
-40C to +85C
-40C to +125C
Description:
The Microchip Technology Inc. 24AA256/24LC256/
24FC256 (24XX256*) is a 32K x 8 (256 Kbit) Serial
Electrically Erasable PROM, capable of operation
across a broad voltage range (1.7V to 5.5V). It has
been developed for advanced, low-power applications
such as personal communications or data acquisition.
This device also has a page write capability of up to 64
bytes of data. This device is capable of both random
and sequential reads up to the 256K boundary.
Functional address lines allow up to eight devices on
the same bus, for up to 2 Mbit address space. This
device is available in the standard 8-pin plastic DIP,
SOIC, TSSOP, MSOP and DFN packages.
100 kHz for V
CC
< 2.5V.
400 kHz for V
CC
< 2.5V.
Features:
• Single Supply with Operation Down to 1.7V for
24AA256 and 24FC256 Devices, 2.5V for
24LC256 Devices
• Low-Power CMOS Technology:
- Active current 400 uA, typical
- Standby current 100 nA, typical
• 2-Wire Serial Interface, I
2
C
™
Compatible
• Cascadable up to Eight Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 5 ms max.
• Self-Timed Erase/Write Cycle
• 64-Byte Page Write Buffer
• Hardware Write-Protect
• ESD Protection >4000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 years
• Factory Programming Available
• Packages Include 8-lead PDIP, SOIC, DFN,
TSSOP and MSOP
• Pb-Free and RoHS Compliant
Block Diagram
A0 A1A2 WP
HV Generator
I/O
Control
Logic
Memory
Control
Logic
XDEC
EEPROM
Array
Page Latches
I/O
SCL
YDEC
SDA
V
CC
V
SS
Sense Amp.
R/W Control
Package Types
PDIP/SOIC
A0
A1
A2
V
SS
1
24XX256
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
A0
A1
A2
V
SS
TSSOP/MSOP*
1
24XX256
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
A0
A1
A2
V
SS
1
24XX256
2
3
4
DFN
8 V
CC
7 WP
6 SCL
5 SDA
Note:
* Pins A0 and A1 are no connects for the MSOP package only.
*24XX256 is used in this document as a generic part number for the 24AA256/24LC256/24FC256 devices.
2010 Microchip Technology Inc.
DS21203Q-page 1
24AA256/24LC256/24FC256
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(†)
V
CC
.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. V
SS
......................................................................................................... -0.6V to V
CC
+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins
4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
V
CC
= +1.7V to 5.5V
Automotive (E): V
CC
= +2.5V to 5.5V
Min.
—
0.7 V
CC
—
0.05 V
CC
Max.
—
—
0.3 V
CC
0.2 V
CC
—
Units
—
V
V
V
V
—
—
V
CC
2.5V
V
CC
< 2.5V
V
CC
2.5V
(Note)
T
A
= -40°C to +85°C
T
A
= -40°C to +125°C
Conditions
DC CHARACTERISTICS
Param.
No.
Sym.
—
D1
D2
D3
V
IH
V
IL
V
HYS
Characteristic
A0, A1, A2, SCL, SDA
and WP pins:
High-level input voltage
Low-level input voltage
Hysteresis of Schmitt
Trigger inputs
(SDA, SCL pins)
Low-level output voltage
Input leakage current
Output leakage current
Pin capacitance
(all inputs/outputs)
D4
D5
D6
D7
D8
D9
V
OL
I
LI
I
LO
C
IN
,
C
OUT
I
CC
Write
I
CCS
—
—
—
—
—
—
—
0.40
±1
±1
10
400
3
1
V
A
A
pF
A
mA
A
I
OL
= 3.0 ma @ V
CC
= 4.5V
I
OL
= 2.1 ma @ V
CC
= 2.5V
V
IN
= V
SS
or V
CC
, WP = V
SS
V
IN
= V
SS
or V
CC
, WP = V
CC
V
OUT
= V
SS
or V
CC
V
CC
= 5.0V
(Note)
T
A
= 25°C, F
CLK
= 1 MHz
V
CC
= 5.5V, SCL = 400 kHz
V
CC
= 5.5V
T
A
= -40°C to +85°C
SCL = SDA = V
CC
= 5.5V
A0, A1, A2, WP = V
SS
T
A
= -40°C to +125°C
SCL = SDA = V
CC
= 5.5V
A0, A1, A2, WP = V
SS
I
CC
Read Operating current
Standby current
—
5
A
Note:
This parameter is periodically sampled and not 100% tested.
DS21203Q-page 2
2010 Microchip Technology Inc.
24AA256/24LC256/24FC256
TABLE 1-2:
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
V
CC
= +1.7V to 5.5V
Automotive (E): V
CC
= +2.5V to 5.5V
Characteristic
Clock frequency
Min.
—
—
—
—
4000
600
600
500
4700
1300
1300
500
—
—
—
—
—
4000
600
600
250
4700
600
600
250
0
250
100
100
4000
600
600
250
4000
600
600
4700
1300
1300
Max.
100
400
400
1000
—
—
—
—
—
—
—
—
1000
300
300
300
100
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Units
kHz
T
A
= -40°C to +85°C
T
A
= -40°C to +125°C
Conditions
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V 24FC256
2.5V
V
CC
5.5V 24FC256
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V 24FC256
2.5V
V
CC
5.5V 24FC256
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V 24FC256
2.5V
V
CC
5.5V 24FC256
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
5.5V 24FC256
All except, 24FC256
1.7V
V
CC
5.5V 24FC256
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V 24FC256
2.5V
V
CC
5.5V 24FC256
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V 24FC256
2.5V
V
CC
5.5V 24FC256
(Note 2)
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
5.5V 24FC256
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V 24FC256
2.5V
V
CC
5.5V 24FC256
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
5.5V 24FC256
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
5.5V 24FC256
AC CHARACTERISTICS
Param.
No.
1
Sym.
F
CLK
2
T
HIGH
Clock high time
ns
3
T
LOW
Clock low time
ns
4
T
R
SDA and SCL rise time
(Note 1)
SDA and SCL fall time
(Note 1)
ns
5
6
T
F
ns
ns
T
HD
:
STA
Start condition hold time
7
T
SU
:
STA
Start condition setup time
ns
8
9
T
HD
:
DAT
Data input hold time
T
SU
:
DAT
Data input setup time
ns
ns
10
T
SU
:
STO
Stop condition setup time
ns
11
T
SU
:
WP
WP setup time
ns
12
T
HD
:
WP
WP hold time
ns
Note 1:
2:
3:
4:
Not 100% tested. C
B
= total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a T
I
specification for standard operation.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site
at www.microchip.com.
2010 Microchip Technology Inc.
DS21203Q-page 3
24AA256/24LC256/24FC256
AC CHARACTERISTICS (Continued)
Param.
No.
13
Sym.
T
AA
Characteristic
Output valid from clock
(Note 2)
Electrical Characteristics:
Industrial (I):
V
CC
= +1.7V to 5.5V
Automotive (E): V
CC
= +2.5V to 5.5V
Min.
—
—
—
—
4700
1300
1300
500
10 + 0.1CB
Max.
3500
900
900
400
—
—
—
—
250
250
50
5
—
Units
ns
T
A
= -40°C to +85°C
T
A
= -40°C to +125°C
Conditions
1.7 V
V
CC
2.5V
2.5 V
V
CC
5.5V
1.7V
V
CC
2.5V 24FC256
2.5 V
V
CC
5.5V 24FC256
1.7V
V
CC
2.5V
2.5V
V
CC
5.5V
1.7V
V
CC
2.5V 24FC256
2.5V
V
CC
5.5V 24FC256
All except, 24FC256
(Note 1)
14
T
BUF
Bus free time: Time the bus
must be free before a new
transmission can start
Output fall time from V
IH
minimum to V
IL
maximum
C
B
100 pF
Input filter spike suppression
(SDA and SCL pins)
Write cycle time (byte or
page)
Endurance
ns
15
T
OF
ns
16
17
18
Note 1:
2:
3:
4:
T
SP
T
WC
—
—
—
1,000,000
ns
ms
All except, 24FC256
(Notes 1
and 3)
—
cycles Page mode, 25°C, 5.5V
(Note 4)
Not 100% tested. C
B
= total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined T
SP
and V
HYS
specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a T
I
specification for standard operation.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site
at www.microchip.com.
FIGURE 1-1:
BUS TIMING DATA
5
2
D3
4
SCL
SDA
IN
7
6
16
3
8
9
10
13
SDA
OUT
(protected)
(unprotected)
14
WP
11
12
DS21203Q-page 4
2010 Microchip Technology Inc.
24AA256/24LC256/24FC256
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Name
A0
A1
(NC)
A2
V
SS
SDA
SCL
(NC)
WP
V
CC
PIN FUNCTION TABLE
8-pin
PDIP
1
2
—
3
4
5
6
—
7
8
8-pin
SOIC
1
2
—
3
4
5
6
—
7
8
8-pin
TSSOP
1
2
—
3
4
5
6
—
7
8
8-pin
MSOP
—
—
1, 2
3
4
5
6
—
7
8
8-pin
DFN
1
2
—
3
4
5
6
—
7
8
Function
User Configurable Chip Select
User Configurable Chip Select
Not Connected
User Configurable Chip Select
Ground
Serial Data
Serial Clock
Not Connected
Write-Protect Input
+1.7V to 5.5V (24AA256)
+2.5V to 5.5V (24LC256)
+1.7V to 5.5V (24FC256)
2.1
A0, A1, A2 Chip Address Inputs
2.3
Serial Clock (SCL)
The A0, A1 and A2 inputs are used by the 24XX256 for
multiple device operations. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
For the MSOP package only, pins A0 and A1 are not
connected.
Up to eight devices (two for the MSOP package) may
be connected to the same bus by using different Chip
Select bit combinations. These inputs must be
connected to either V
CC
or V
SS
.
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed.
This input is used to synchronize the data transfer to
and from the device.
2.4
Write-Protect (WP)
This pin must be connected to either V
SS
or V
CC
. If tied
to V
SS
, write operations are enabled. If tied to V
CC
,
write operations are inhibited but read operations are
not affected.
3.0
FUNCTIONAL DESCRIPTION
2.2
Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open drain
terminal. Therefore, the SDA bus requires a pull-up
resistor to V
CC
(typical 10 k for 100 kHz, 2 k for
400 kHz and 1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
The 24XX256 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access, and
generates the Start and Stop conditions while the
24XX256 works as a slave. Both master and slave can
operate as a transmitter or receiver, but the master
device determines which mode is activated.
2010 Microchip Technology Inc.
DS21203Q-page 5
Microcontroller MCU
京公网安备 11010802033920号
EEWORLD
