CD4073B, CD4081 B, CD4082B Types
COS/MOS AND Gates
High-Voltage Types (20-Volt Rating)
Features:
•
•
•
Medium-Speed Operation - tpLH'
tpHL = 60 ns (typ.) at VDD = 10 V
100% tested for quiescent current at 20 V
Maximum input current of 1 p,A at 18 V over
full package-temperature range; 100 nA at
18 V and 25
0
C
Noise margin (full package-temperature
range) =
1 Vat VDD = 5 V
2 Vat VDD = 10 V
2.5 V at VDD "15 V
Standardized, symmetrical output
characteristics
5-V, 10-V, and 15·V parametric ratings
Meets all requirements of JEDEC Tentative
Standard No. 13A, "Standard Specifications
for Description of '8' Series CMOS Devices"
CD4073B Triple 3-1 nput AN D Gate
CD4081 B Quad 2-lnput AND Gate
CD4082B Dual 4-lnput AND Gate
The OCA-CD4073B, CD4081B and CD·
4082B AN 0 gates provide the system de-
signer with direct implementation of the
AND function and supplement the existing
family of COS/MOS gates.
The CD4073B, C04081 Band C04082B
types are supplied in 14-lead dual-in-
line ceramic packages (0 and F suffixes),
14-lead dual-in-line plastic packages (E
suffix). 14-lead ceramic flat packages (K
suffix). and in chip form (H suffix).
•
•
•
•
CD4081B
FUNCTIONAL DIAGRAM
MAXIMUM RATINGS,
Absolute-Maximum Values:
DC SUPPLY·VOLTAGE RANGE, (V DO)
(Voltages referenced to VSS Terminal)
-0.5
to +20 V
INPUT VOLTAGE RANGE, ALL INPUTS
-0.5
to VDD +0.5 V
±10mA
DC INPUT CURRENT, ANY ONE INPUT
POWER DISSIPATION PER PACKAGE (Pol.
For T A
=
-40 to +60 o C (PACKAGE TYPE E)
. . . . . . • ..
500mW
Derate Lmearly at 12 mW/oC to 200 mW
For T A
=
+60 to +85 0 C IPACKAGE TYPE E)
For T A
=
-55 to + 100°C (PACKAGE TYPES D,F)
. . . . . . . ..
500mW
Derate Lmearly at 12 mW/oC to 200 mW
For T A
=
+100 to +125
0
C IPACKAGE TYPES 0, Fl
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
100mW
FOR TA
=
FULL PACKAGE·TEMPERATURE RANGE (All Package Types)
OPERATING·TEMPERATURE RANGE (T A)
-55 to+1250C
PACKAGE TYPES D, F, H
PACKAGE TYPE E . . . . . . .
-40 to +85 0C
STORAGE TEMPERATURE RANGE (T stg )
-65 to +1500 C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16
±
1/32 Inch (1.59
±
0.79 mm) from case for lOs max.
B
A
9
F
10
II
G
12
CD4082S
FUNCTIONAL DIAGRAM
RECOMMENDED OPERATING CONDITIONS
For maximum reliability, nominal operating conditions should
be
selected so that
operation is always within the fol/owing ranges:
CHARACTERISTIC
Supply-Voltage Range (For T A = Full Package
Temperature Range)
LIMITS
MIN.
MAX.
UNITS
V
A
3
18
DYNAMIC ELECTRICAL CHARACTERISTICS at T A=25
0
C, Input t r ,tf=20 ns,
and CL =50 pF, RL =200 kn
TEST CONDITIONS
VDD
Volts
Propagation Delay Time,
tpHL, tpLH
TranSition Time,
tTHL, tTLH
Input CapaCitance, CIN
Any Input
ALL TYPES
LIMITS
TYP.
MAX.
B 2
C 8
o
E
3
(,
CHARACTERISTIC
UNITS
.
l
F '
10
5
10
15
5
10
15
125
60
45
100
50
40
5
250
120
90
200
100
80
7.5
ns
ns
pF
CD4073B
FUNCTIONAL DIAGRAM
-
242
CD4073B, CD4081B, CD4082B Typ
s
STATIC ELECTRICAL CHARACTERISTICS
CONDITIONS
Vo
(V)
VIN
(V)
VDD
(V)
LIMITS AT II
~[
IICATED TEMPERATURES (oC)
Values at
-55,
i-
2
!i,
+125
Apply to O,F ,H Packages
Values at
-40, +2
!;,
+85
Apply to E Package
CHAI~AC
HR-
ISTIC
+25
-55
025
0.5
1
5
064
-40
0.25
0.5
1
5
061
UNITS
+
:~5
i'.5
15
+125
75
15
30
150
0.36
0.9
2.4
-036
-1.15
-0.9
-24
Min.
Typ.
Max.
Quiescent
0
eVlce
Current,
looMa
~.-
Output Lov
,
(Sin'tlCu rrent
IOLMi
11.
Output Hig
(Source)
Current,
IOHM in.
Output Vo Itage:
Low·Lev! I,
VOLM
ax.
Output Vo Itage:
H,gh·Lev
HI,
VOIi M,r
I
Input Low
Voltage,
V,L
M
,IX.
Input High
Voltage,
V,H
M
In.
Input Curr
~nt
liN
Max.
-
-
-
-
04
0.5
1.5
4.6
2.5
9.5
13.5
0,5
0,10
0,15
0,20
0,5
0,10
0,15
0,5
0,5
0,10
0,15
0,5
0,10
0,15
0,5
0,10
0,15
5
10
15
20
5
10
15
5
5
10
15
5
10
15
5
10
15
5
10
15
5
10
15
18
-
-
-
-
0.Q1
001
0.01
002
1
26
68
-1
-32
-26
-6.8
0
0
0
5
10
15
0.25
0.5
1
5
JJ.A
:30
50
o
42
1.1
051
1.3
34
-0.51
-16
-1.3
-3.4
-
-
INPUT VOLTAGE (V'N'- V
.,
1.5
1.6
4
4.2
-0.64 -0.61
-1.8
-2
-1.6 -1.5
-4
-42
.'8
() 42
1.3
11
2.8
-
-
Fig.
3 -
Typical voltage transfer characteristics.
rnA
-
-
-
0.05
005
005
-
-
-
-
-
-
0.5
1
1.5
0.5,4.5
1,9
1.5,13.5
14 91
,
15
0.0
5
0.1l
5
0.1l
5
4.9
5
9.!l
5
-
-
-
4.95
9.95
14.95
-
-
-
15
3
4
V
-
-
-
-
-
-
0,18
-
-
-
-
:1
4
3.
5
LOAD CAPACITANCE eCl' -
p"
-
3.5
7
11
-
-
-
:'
11
±O 1
±0.1
±1
±1
-
:!:10- 5
-
-
-
±0.1
V
Fig.
4 -
Typical propagation delay time
as a function of load capacitence.
-
JJ.A
""",Jl:
~J-rf
~]
nd nd
1({j,__.
V
1
v~s
3)
a
~~~tvss
3(4,10,1 )
:u
10
DRAIN-TO-SOURCE VOLTAGE IVDS'-V
Fig.
5 -
Typical output low (sink)
current characteristics.
II ALL INPUTS ARE
PROTECTEO BY
COS/MOS PROTECTION
NETWORK
Fig.
1 -
Schematic diagram for CD4081 B
(1
of
4
identical gates).
/~,)
Fig.
2 -
Logic diagram for CD4081 B
(1
of
4
Identical gates).
DRAIN-TO-SOURCE IIOLTAGE (VDS'-V
Fig.
6 -
Mmimum output low (smk)
current characteristics.
___________________________________________ 243
CD4073B, CD4081B, CD4082BTyp
s
VOO
DRAIN-TO-SOURCE VOLTAGE
(Vosl-V
' ' '1'
+-----=+-----.
211210---1-4
VSS
*
ALL INPUTS ARE PROTECTED
BY
CDS/ MOS PROTECTION NETWORK
Fig.
8 -
£f
q,,,
Fig.
7 -
Schematic diagram for CD40828
(1
of
2
identical gates).
11131
Typical output high (source)
current charactertstics.
DRAIN-TO-SDUact VOLTAGf:
(VDa)-V
Fig. 10
-
Minimum output high (source)
current characteristics.
Fig.
9 -
Logic diagram for CD40828
(1
of
2
identical gates).
voo
S(S,III
*
1(4~'121
2(3,131
*
1-=-4---\----1
Fig,
12 -
Typical transition time as a
function of load capacitance.
2~'C
ID"~
Vss
*
ALL INPUTS ARE PROTECTED SY
COS/MOS PROTECTION NETWORK
~
•
t'
~
~
.
2
4
AMBIEHT
TEMPERATURE (TA)'
10':
Fig.
11 -
Schematic diagram for CD40738
(1
of
3
identical gates).
~
IO'x
ii
i
02.
2
.
4
2
.Ii
1/ ....
V
1;9~
oI?.,ol
~71/
II I
11V
V . .
II
~,,~~
~V
V"
[/1/ ....
V
c...~.F
i
2
10
10
10 2
INPUT FREQU[NCY
(f
11-
kH.
.
CL.15 pF ---
II
r ••
I II
•
10'
Fig.
14 -
Fig.
13 -
Logic diagram for CD40738
(1
of
3
identical gates).
Typical dynamic power dissi·
pation par gate as a function
of frequency.
244 __________________________________________________________________
II
CD4073B, CD4081B, CD4082BTyp
s
INPUTS
o
Vss
Vss
92CS-2140IRI
Fig.
15 -
Ouiescent devIce current test circuit.
INPUOS
Veo
Veo
'-0-.
o
N~E
\Y"'"
Vss
MEASURE INPUTS
SEOUENTIALLY.
TO eoTH VDD AND VSS
CONNECT ALL UNUSED
INPUTS TO EITHER
VDD
OR
VSS
VSS
Dimensions and pad lavout
~-----------(-1~=~~2-'--------~
for CD4081 B.
Fig.
16 -
Input current test circuit.
•
I
I
1
~7-
65
(I 441-1
6~11
Fig.
17 -
Input·voltage test circuit.
TERMINAL ASSIGNMENTS
14
13
12
10
9
TOP VIEW
voo
J·A
B
K.C 0
C
D
Vss
0;_"';0"'
,M
pod
M'G
H
L'E
F
for CD4082B.
"YO~"".>--
________---,:
o
CD4081B
J'A BCD
I.
14
o
C
A
~C
2
13
12
II
VOD
K.E
F G H
ID
VSS--...'-----_-"-'-IC
TOP VIE ..
The photographs and dImenSIons
of each COS/MaS chip represent
a chIp when it is part of the wafer.
When the wafer IS cut into ChIPS,
the cleavage angles are
5,0
Instead
of
900
with respect to the face of
the chip. Therefore, the isolated
chip is actuallv
7
mils (0.
17
mm)
larger In both dimensions.
Dimensions in parentheses are In
millimeters and are de"ved from
the baSIC inch dimensions as in-
dIcated. Grid graduations are in
mils (10- 3 Inch).
CD4082B
lC' INTER NAL CONNECTION-
DO NOT USE
14
13
12
II
10
K'O E F
Vss
TOP VIEW
VOO
G
.~
L'G H I
J.A B C
C
DImenSIons and pad favout
for CD4073B
f4------------(
1-"'.
I
-70-II---------~
59-67
92CS-292'6
92(5-24';)38
CD4073B
___________________________________________ 245
GD32 MCU
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