INTEGRATED CIRCUITS
DATA SHEET
TDA9851
I
2
C-bus controlled economic BTSC
stereo decoder
Product specification
File under Integrated Circuits, IC02
1997 Nov 12
Philips Semiconductors
Product specification
I
2
C-bus controlled economic BTSC stereo
decoder
FEATURES
•
Voltage Controlled Amplifier (VCA) noise reduction
circuit
•
Stereo or mono selectable at the AF outputs
•
Stereo pilot PLL circuit with ceramic resonator
•
Automatic pilot cancellation
•
Automatic Volume Level (AVL) control (+6 to
−15
dB)
•
I
2
C-bus transceiver.
GENERAL DESCRIPTION
The TDA9851 is a bipolar-integrated BTSC stereo
decoder for application in TV sets, VCRs and multimedia
PCs.
QUICK REFERENCE DATA
SYMBOL
V
CC
I
CC
V
o(rms)
PARAMETER
supply voltage
supply current
output voltage (RMS value)
composite input voltage
250 mV (RMS) for
100% modulation L + R
(25 kHz deviation); f
mod
= 300 Hz
14% modulation; f
L
= 300 Hz;
f
R
= 3 kHz
100% modulation L or R;
f
mod
= 1 kHz
mono mode; referenced to 500 mV
output signal
CCIR 468-2 weighted;
quasi peak
DIN noise weighting filter
(RMS value)
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
TDA9851
TDA9851T
SDIP24
SO24
DESCRIPTION
plastic shrink dual in-line package; 24 leads (400 mil)
plastic small outline package; 24 leads; body width 7.5 mm
50
−
60
73
CONDITIONS
MIN.
8
−
−
TYP.
9
30
500
TDA9851
MAX.
9.5
40
−
UNIT
V
mA
mV
α
csL,R
THD
L,R
S/N
stereo channel separation
L and R
total harmonic distortion L and R
signal-to-noise ratio
−
−
20
0.2
−
1.0
dB
%
−
−
dB
dBA
VERSION
SOT234-1
SOT137-1
1997 Nov 12
2
book, full pagewidth
1997 Nov 12
C3
C4
C6
n.c.
CP2
CER
4
8
12
13
9
11
16
6
3
CPH
CMO
CAV
CSS
R1
Q1
C5
C7
L
+
R
DEMATRIX
AND
MODE SELECT
AUTOMATIC
VOLUME
LEVEL
OUTL
OUTR
L
−
R
BLOCK DIAGRAM
Philips Semiconductors
C2
CP1
5
composite
baseband
input
COMP
7
STEREO DECODER
C1
FDI
21
TDA9851
24
SUPPLY
I
2
C-BUS
TRANSCEIVER
I
2
C-bus controlled economic BTSC stereo
decoder
3
FILTER
AND
REFERENCE
18
CW
C11
VCC
C13
C14
C15
TW
VCAP AGND Vref
17
2
15
22
14
10
RFR
R4
R2
SDA
1
FDO 20
DETECTOR
AND
VOLTAGE
CONTROLLED
AMPLIFIER
SCL
R3
23
DGND
19
C9
BPU
C10
MHA969
Product specification
TDA9851
Fig.1 Block diagram.
Philips Semiconductors
Product specification
I
2
C-bus controlled economic BTSC stereo
decoder
TDA9851
Component list
Electrolytic capacitors
±20%;
foil capacitors
±10%;
resistors
±5%;
unless otherwise specified; see Fig.1.
COMPONENT
C1
C2
C3
C4
C5
C6
C7
C9
C10
C11
C13
C14
C15
R1
R2
R3
R4
Q1
VALUE
2.2
µF
220 nF
2.2
µF
220 nF
2.2
µF
2.2
µF
4.7
µF
22 nF
4.7 nF
1
µF
10
µF
100
µF
100
µF
3.3 kΩ
15 kΩ
1.3 kΩ
100 kΩ
CSB503F58
CSB503JF958
radial leads
alternative as SMD
foil
electrolytic
foil
electrolytic
electrolytic
electrolytic
foil
foil
electrolytic
electrolytic
electrolytic
electrolytic
63 V
63 V
16 V
16 V
63 V
63 V
63 V
±10%
63 V
TYPE
electrolytic
63 V
REMARK
1997 Nov 12
4
Philips Semiconductors
Product specification
I
2
C-bus controlled economic BTSC stereo
decoder
PINNING
SYMBOL PIN
SCL
V
CC
C
PH
CER
C
P1
C
P2
COMP
C
MO
C
SS
R
FR
n.c.
OUTL
OUTR
V
ref
V
CAP
C
AV
TW
C
W
BPU
FDO
FDI
AGND
DGND
SDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DESCRIPTION
serial clock input (I
2
C-bus)
supply voltage
capacitor for phase detector
ceramic resonator
capacitor for pilot detector
capacitor for pilot detector
composite input signal
capacitor DC-decoupling mono
capacitor DC-decoupling stereo
resistor for filter reference
not connected
output, left channel
output, right channel
reference voltage 0.5V
CC
capacitor for electronic filtering of
supply
automatic volume control capacitor
capacitor timing
capacitor for VCA and band-pass filter
lower corner frequency
band-pass filter upper corner
frequency
fixed de-emphasis output
fixed de-emphasis input
analog ground
digital ground
serial data input/output (I
2
C-bus)
Fig.2 Pin configuration.
handbook, halfpage
TDA9851
SCL 1
VCC 2
CPH 3
CER 4
CP1 5
CP2 6
24 SDA
23 DGND
22 AGND
21 FDI
20 FDO
19 BPU
TDA9851
COMP 7
CMO 8
CSS 9
RFR 10
n.c. 11
OUTL 12
MHA968
18 CW
17 TW
16 CAV
15 VCAP
14 Vref
13 OUTR
1997 Nov 12
5