TECHNICAL NOTE
Power Management LSI Series for Automotive Body Control
Voltage Detector ICs
with Watchdog Timer
BD37A19FVM，BD37A41FVM，BD87A28FVM，BD87A29FVM
BD87A34FVM，BD87A41FVM，BD99A41F
Description
The BD37A19FVM,BD37A41FVM,BD87A28FVM,BD87A29FVM,BD87A34FVM,BD87A41FVM,BD99A41F is a watchdog timer reset IC. It
delivers a high precision detection voltage of
±1.5%
and a super-low current consumption of 5
µA
(Typ.). It can be used in a wide range of
electronic devices to monitor power supply voltages and in system operation to prevent runaway operation.
Features
1) High precision detection voltage:
±1.5%, ±2.5%
(Ta =
−40°C
to 105°C)
2) Super-low current consumption: 5
µA
(Typ.)
3) Built-in watchdog timer
4) Reset delay time can be set with the CT pin's external capacitance.
5) Watchdog timer monitor time and reset time can be set with the CTW pin's external capacitance.
6) Output circuit type: N-channel open drain
7) Package: MSOP8(BD37A□□FVM,BD87A□□FVM)／SOP8(BD99A41F)
Applications
All devices using microcontrollers or DSP, including vehicle equipment, displays, servers, DVD players, and telephone systems.
Product line
INH logic
Model
Detection voltage
H: Active
BD37A□□FVM
1.9 V/4.1V
BD99A41F
4.1 V
L: Active
BD87A□□FVM
2.8V/2.9V/3.4 V/4.1V
●Absolute
maximum ratings
(Ta = 25°C)
Parameter
Power supply voltage
CT pin voltage
CTW pin voltage
RESET pin voltage
INH pin voltage
CLK pin voltage
Power dissipation
Operating ambient temperature
Storage temperature
Maximum junction temperature
*1
*2
SOP8
Symbol
VDD
VCT
VCTW
VRESET
VINH
VCLK
Pd
Topr
Tstg
Tjmax
Limit
−0.3
to 10
−0.3
to VDD + 0.3
−0.3
to VDD + 0.3
−0.3
to VDD + 0.3
−0.3
to VDD + 0.3
−0.3
to VDD + 0.3
470*1
550*2
−40
to + 105
−55
to + 125
125
Unit
V
V
V
V
V
V
mW
°C
°C
°C
MSOP8 : Reduced by 4.70 mW/°C over 25°C, when mounted on a glass epoxy board (70 mm
×
70 mm
×
1.6 mm).
: Reduced by 5.50 mW/°C over 25°C, when mounted on a glass epoxy board (70 mm
×
70 mm
×
1.6 mm).
Ver.B July 2006
●Recommended
operating ranges
(Ta =
−40°C
to 105°C)
Parameter
RESET power supply voltage
WDT power supply voltage
Symbol
VDD RESET
VDD WDT
Min.
1.0
2.5
Max.
10
10
Unit
V
V
●Electrical
characteristics
(Unless otherwise specified, Ta =
−40°C
to 105°C, VDD = 5 V)
Parameter
[Overall]
Total supply current 1
(during WDT operation)
Total supply current 2
(when WDT stopped)
Output leak current
Output current capacity
[RESET]
1.9V Detect
Detection
voltage 1
2.8V Detect
2.9V Detect
3.4V Detect
4.1V Detect
1.9V Detect
Detection
voltage 2
2.8V Detect
2.9V Detect
3.4V Detect
4.1V Detect
1.9V Detect
Hysteresis
width
2.8V Detect
2.9V Detect
3.4V Detect
4.1V Detect
RESET transmission delay
time: low
→
high
Delay circuit resistance
Delay pin threshold voltage
Delay pin output current
Min. operating voltage
[WDT]
WDT monitor time
WDT reset time
Clock input pulse width
CLK high threshold voltage
CLK low threshold voltage
CLK high threshold voltage
CLK low threshold voltage
CTW charge current
CTW discharge current
TwH
TwL
TWCLK
VCLKH
VCLKL
VINHH
VINHL
ICTWC
ICTWO
7.0
2.4
500
VDD
×
0.8
0
VDD
×
0.8
0
0.25
0.75
Rrst = 10 MΩ
ICTWC = 0.5
µA
ICTWO = 1.5
µA
10.0
3.3
—
—
—
—
—
0.50
1.50
(Typ.)
(Typ.)
(Typ.)
20.0
7.0
—
VDD
VDD
×
0.3
VDD
VDD
×
0.3
0.75
2.00
ms
ms
ns
V
V
V
V
µA
µA
VCTW = 0.2 V
VCTW = 0.8 V
CTW = 0.01
µF
*2
CTW = 0.01
µF
*3
VDET1
VDET1
VDET1
VDET1
VDET1
VDET2
VDET2
VDET2
VDET2
VDET2
Vrhys
Vrhys
Vrhys
Vrhys
Vrhys
TPLH
Rrst
VCTH
ICT
VOPL
1.871
2.758
2.886
3.349
4.039
1.852
2.730
2.857
3.315
4.007
VDET
×
0.03
VDET
×
0.018
VDET
×
0.02
VDET
×
0.02
VDET
×
0.018
3.9
5.8
VDD
×
0.3
150
1.0
1.900
2.800
2.930
3.400
4.100
1.900
2.800
2.930
3.400
4.100
VDET
×
0.13
VDET
×
0.045
VDET
×
0.05
VDET
×
0.05
VDET
×
0.035
6.9
10.0
VDD
×
0.45
—
—
1.929
2.842
2.974
3.451
4.162
1.948
2.870
3.003
3.485
4.202
VDET
×
0.19
VDET
×
0.060
VDET
×
0.06
VDET
×
0.07
VDET
×
0.050
10.1
14.5
VDD
×
0.6
—
—
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
ms
MΩ
V
µA
V
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta =
−40
to 105°C
Ta =
−40
to 105°C
Ta =
−40
to 105°C
Ta =
−40
to 105°C
Ta =
−40
to 105°C
Ta =
−40
to 105°C
Ta =
−40
to 105°C
Ta =
−40
to 105°C
Ta =
−40
to 105°C
Ta =
−40
to 105°C
CT = 0.001
µF
*1
When VDD = VDET
±0.5
V
VCT = GND
RL = 470 KΩ
VDD = 1.50 V, VCT = 0.5 V
VOL
≤
0.4 V, RL = 470 KΩ
IDD1
IDD2
Ileak
IOL
—
—
—
0.7
5
5
—
—
14
14
1
—
µA
µA
µA
mA
INH : WDT ON Logic Input
CTW = 0.1
µF
INH : WDT OFF Logic Input
VDD = VDS = 10 V
VDD = 1.2 V, VDS = 0.5 V
Symbol
Limit
Min.
Typ.
Max.
Unit
Conditions
*1 TPLH can be varied by changing the CT capacitance value.
TPLH (s)
≈
0.69
×
Rrst (MΩ)
×
CT (µF)
TwH (s)
≈
(0.5
×
CTW (µF))/ICTWC (µA)
TwL (s)
≈
(0.5
×
CTW (µF))/ICTWO (µA)
Note: This IC is not designed to be radiation-resistant.
*2 TwH can be varied by changing the CT capacitance value.
*3 TwL can be varied by changing the CTW capacitance value.
2/8
●Reference
data
(Unless otherwise specified, Ta = 25°C) : 4.1V Detection
12
10
1400
OUTPUT VOLTAGE: VOUT [V]
8
CT PIN CURRENT: ICT [µA]
10
8
6
4
2
0
0
2
4
6
8
10
CIRCUIT CURRENT: IDD [µA]
Ta=105°C
1200
1000
800
600
400
200
0
6
4
Ta=25°C
Ta=−40°C
2
0
0
2
4
6
8
10
0
1
2
3
4
5
SUPPLY VOLTAGE: VDD [V]
SUPPLY VOLTAGE: VDD [V]
CT PIN VOLTAGE: VCT [V]
Fig. 1
2
1.5
1
0.5
0
-0.5
-1
0
1
Detection Voltage
2
Fig. 2
Total Supply Current
10000
Fig. 3
Delay Pin Current vs
Power Supply Voltage
Ta=105°C
1.5
OUTPUT DELAY TIME: TPLH [ms]
10
RESET CURRENT: IRESET [mA]
CTW PIN CURRENT: ICTW [µA]
1000
1
Ta=−40°C
Ta=25°C
100
0.5
10
0
0
2
4
6
8
2
3
4
5
1
0.0001
0.001
0.01
0.1
CTW PIN VOLTAGE: VCTW [V]
RESET VOLTAGE: VRESET [V]
CT PIN CAPACITY : CT [µF]
Fig. 4
CTW Charge Discharge Current
Fig. 5
Output Current
Fig. 6
RESET Transmission Delay
Time vs Capacitance
10000
5
1
DETECTION VOLTAGE: VDET [V]
1000
4.75
4.5
OPERATING VOLTAGE: VOPL [V]
80
WDT RESET TIME: Tw [ms]
0.75
100
Monitor time
L
→
H
4.25
4
3.75
3.5
-40
0.5
10
Reset time
リセット時間
1
H
→
L
0.25
0.1
0.001
0.01
0.1
1
10
0
40
0
-40
0
40
80
CTW PIN CAPACITY : CTW[µF]
CT PIN VOLTAGE: VCT [V]
AMBIENT TEMPERATURE: Ta [
℃
]
AMBIENT TEMPERATURE: Ta [
℃
]
Fig. 7
OUTPUT DELAY RESISTANCE: Rrst [MΩ]
13
WDT Time vs Capacitance
Fig. 8
Detection Voltage vs Temperature
Fig. 9
Operating Marginal Voltage vs
Temperature
10
12
15
OUTPUT DELAY TIME: TPLH [ms]
9
WDT RESET TIME: Tw [ms]
12
Monitor time
監視時間
11
8
9
10
7
6
Reset time
リセット時間
9
6
3
8
-40
0
40
80
AMBIENT TEMPERATURE: Ta [℃]
5
-40
0
40
80
0
-40
0
40
80
AMBIENT TEMPERATURE: Ta [
℃
]
AMBIENT TEMPERATURE: Ta [
℃
]
Fig. 10
CT Pin Circuit Resistance vs
Temperature
Fig. 11
RESET Transmission Delay
Time vs Temperature
Fig. 12
WDT Time vs Temperature
3/8
●Block
diagram
BD37A□□FVM
BD87A□□FVM／BD99A41F
VDD
RESET
CLK
1
R
8
CTW
1
R
Q
Vref
INH
2
VDD
7
CT
2
VDD
VDD
8
RESET
+
Vref
CT
S
+
S
Q
N.C.
7
CTW
3
Pulse
generation
circuit
+
+
VthH
VthL
R
S
Q
6
GND
CLK
3
+
+
VthH
VthL
R
S
Q
INH
6
Pulse
generation
circuit
GND
4
VDD
N.C.
4
5
VDD
5
CT pin capacitor: 470 pF to 3.3
µF
CTW pin capacitor: 0.001
µF
to 10
µF
Fig.13
●Pin
assignments
8 7 6 5
1 2 3 4
Fig.14
BD37A□□FVM
No.
1
2
3
4
5
6
7
8
Pin
name
CLK
CT
CTW
VDD
N.C.
GND
INH
RESET
Function
Clock input from microcontroller
Reset delay time setting capacitor connection pin
WDT time setting capacitor connection pin
Power supply pin
NC pin
GND pin
WDT on/off setting pin
INH=H/L:WDT=ON/OFF
Reset output pin
7
8
N.C.
RESET
6
INH
No.
1
2
3
4
5
BD87A□□FVM／BD99A41F
Pin
name
CTW
CT
CLK
GND
VDD
Function
WDT time setting capacitor connection pin
Reset delay time setting capacitor connection pin
Clock input from microcontroller
GND pin
Power supply pin
WDT on/off setting pin
INH=H/L:WDT=OFF/ON(BD87A□□FVM)
INH=H/L:WDT=ON/OFF(BD99A41F)
NC pin
Reset output pin
4/8
●I/O
Circuit diagram
CT
VDD
VDD
INH
VDD
CT
VDD
10MΩ(Typ.)
CLK
INH
CT
CTW
VDD
VDD
RESET
RESET
CTW
Fig.15
●Timing
chart
VDD
0
VDETH
VDET
WDT circuit turns off
when INH is low.
VDETH = VDET + Vrhys
(BD37A□□FVM／BD99A41F)
0
INH
WDT circuit turns off
when INH is high.
INH
(BD87A□□FVM)
0
CLK
0
*4 TWCLK TWCLK
VCT VCTH
0
VthH
VCTW
0
VthL
*2
*1
TPLH
TWH
*3
TWL
RESET
0
(1)(2) (3)
(4) (5)
(4) (5)
(6) (7)
(7)
(4) (5) (8)
(9)
(4) (5) (10) (2)(3)
(4) (5) (10) (2)(3)
(4) (5) (10)(11)
Fig.16
●Explanation
(1)
(2)
The RESET pin voltage (RESET) switches to low when the power supply voltage (VDD) falls to 0.8 V.
The external capacitor connected to the CT pin begins to charge when VDD rises above the reset detection voltage (VDETH). The
RESET signal stays low until VDD reaches the VDETH voltage and switches to high when VDD reaches or exceeds the VDETH voltage.
The RESET transmission delay time TPLH allowed to elapse before RESET switches from low to high is given by the following equation:
TPLH (s)
≈
0.69
×
Rrst
×
CT (µF) [1]
Rrst denotes the IC's built-in resistance and is designed to be 10 MΩ (Typ.). CT denotes the external capacitor connected to the CT pin.
The external capacitor connected to the CTW pin begins to charge when RESET rises, triggering the watchdog timer.
The CTW pin state switches from charge to discharge when the CTW pin voltage (VCTW) reaches VthH, and RESET switches from high
to low. The watchdog timer monitor time TWH is given by the following equation:
TWH (s)
≈
(0.5
×
CTW (µF))/(ICTWC) [2]
ICTWC denotes the CTW charge current and is designed to be 0.50
µA
(Typ.). CTW denotes the external capacitor connected to the
CTW pin.
(3)
(4)
5/8
京公网安备 11010802033920号
EEWORLD
