AJAV-5601
W-CDMA/HSPA Band I Power Amplifier
Data Sheet
Description
The AJAV-5601 is a complete, high-performance power
amplifier for W-CDMA and HSPA wireless communica-
tions. Based on a unique, patented architecture, the AJAV-
5601 integrates circuitry for TX filtering, RF coupling,
power regulation, input and output matching and power
control. The PA is powered by a single connection to the
battery and is implemented in a standard CMOS process.
Features
•
High-performance 3G power amplifier
-
UMTS Band I (1920 – 1980 MHz)
-
W-CDMA, HSPA, and HSPA+ Compliant
•
Integrated TX filtering
-
Delivers best noise in the industry
•
Integrated directional coupler
•
Integrated regulators and PA bias
•
Single direct connection to the battery
VBAT
RFO
GND
PAD
CPLI
GND
CPLO
Pin Assignments
Top View (x-ray)
VBAT
RFI
VM1
VM0
VEN
US Patent # 7,728,661; 7,768,350;
7,872,528; 8,022,766
Other patents pending
-
No external switches or isolation inductors
•
High linear efficiency
•
Low average current
•
High capacity CMOS process
•
Small 3
×
3 mm package
Applications
•
Smartphones, data cards and 3G modules
•
Tablets, netbooks and network PCs
•
E-books and wireless electronic readers
Functional Block Diagram
Top View
VBAT
AJAV-5601
REGULATOR / BIAS
RFI
INPUT
MATCH
OUTPUT
MATCH
RFO
CPLI
CPLO
PA
CONTROL
VM0 VM1 VEN
Electrical Characteristics
Table 1. Absolute Minimum and Maximum Ratings
[1]
Parameter
Supply Voltage
[2]
Control Voltage
[3]
RF Input Power
[4]
Electrostatic Discharge (ESD)
[5]
Storage Temperature
T
STG
Human Body Model (HBM)
Symbol
V
BATT
V
CTRL
Condition
V
CTRL
< V
BATT
Min
-0.3
-0.3
-
-
-55
Typ
-
-
-
-
-
Max
4.5
4.5
+10
3.0
125
Unit
V
V
dBm
kV
°C
Notes:
1. Permanent device damage may occur if the ratings above are exceeded. Functional operation is not guaranteed under these conditions and
should be restricted to the recommended operating conditions in Table 2. Exposure to absolute ratings for extended periods may affect device
reliability.
2. Supply voltage is applied to VBAT pin.
3. Control voltages are applied to VEN, VM0, VM1 pins.
4. RF input is applied to RFI, CPLI pins.
5. For all pins.
Table 2. Operating Conditions
[1]
Parameter
Supply Voltage
[2]
Control Voltage – High
[3]
Control Voltage – Low
[3]
Ambient Temperature
Symbol
V
BATT
V
IH
V
IL
T
A
Condition
V
IH
< V
BATT
Min
2.5
1.3
0.0
-30
Typ
3.8
1.8
-
25
Max
4.2
V
BATT
0.5
90
Unit
V
V
V
°C
Notes:
1. To ensure proper operation, the VEN pin should be asserted from V
IL
to V
IH
at least 2
ms
after power is applied to the VBAT pin.
2. Device remains functional down to V
BATT
= 2.5 V. At V
BATT
< 3.4 V, output power is derated by 0.5 dB.
3. Logic states for VEN, VM0, VM1 pins.
Table 3. Mode Control Logic
[1]
Mode
High Power Mode (HP)
Mid Power Mode (MP)
Low Power Mode (LP)
Powerdown
Output Power Range
[2]
16.5 dBm < P
OUT
≤ P
MAX
6.0 dBm < P
OUT
≤ 16.5 dBm
P
OUT
≤ 6.0 dBm
VEN
High
High
High
Low
VM0
Low
High
High
X
VM1
Low
Low
High
X
Notes:
1. The VM0 and VM1 pins are controlled externally to achieve maximum PA efficiency. High and low logic states are specified in Table 2.
2. Maximum linear output power, P
MAX
, is defined in Table 4.
2
Table 4. Electrical Specifications
[1]
Parameter
Frequency
Maximum Linear Output Power
[2]
Symbol
F
RF
P
MAX
Condition
HP mode
MP mode
LP mode
HP mode
MP mode
LP mode
RX Band, 190 MHz offset
GPS Band, 1524 – 1577 MHz
ISM Band, 2400 – 2484 MHz
±
5 MHz offset
±
10 MHz offset
RX Band, 190 MHz offset
GPS Band, 1524 – 1577 MHz
ISM Band, 2400 – 2484 MHz
P
OUT
≤ P
MAX
HP mode
MP mode
LP mode
Fixed battery
Average power tracking
VEN = V
IL
Min
1920
+26.5
+16.0
+5.5
26.5
16.5
6.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-1
-
-
-
-
Typ
-
+27.0
+16.5
+6.0
28.0
18.0
8.0
-15
-35
-34
-42
-53
-146
-154
-156
1.5
40
23
8
25
18
5
7
1.4:1
-
-
-
-
5
-21
-0.7
-0.4
-28
-28
-
12
8
-
-
Max
1980
-
-
-
-
-
-
-
-
-
-38
-48
-
-
-
3.35
-
-
10
-
-
10
10
2.5:1
-31
-41
-35
-35
10
-
-
-
-
-
+1
15
10
-70
10:1
Unit
MHz
dBm
dBm
dBm
dB
dB
dB
dBc
dBc
dBc
dBc
dBc
dBm/Hz
dBm/Hz
dBm/Hz
%
%
%
mA
mA
mA
mA
mA
VSWR
dBc
dBc
dBc
dBc
degree
dB
dB
dB
dB
dB
dB
ms
ms
dBc
VSWR
Gain
[2]
G
RX Band Gain
[2,3]
G
RX
Adjacent Channel Leakage Ratio
[2,4]
Noise
[14]
ACLR1
ACLR2
[5]
N
Error Vector Magnitude
[2,4,5]
Power Added Efficiency
[2,5,6]
Quiescent Idle Current
Average Current
[2,5,7]
Powerdown Current
[4,8]
Logic Current
[4,9]
Input Impedance
[5]
Reverse Intermodulation
[4,5,10]
Harmonics
[2,4,5]
Instantaneous Phase Change
[4,5,15]
Coupling Factor
[11]
Daisy Chain Insertion Loss
[5]
Daisy Chain Return Loss
[5,11]
Output Power Error
[5,12]
Turn-on Time
[13]
Turn-off Time
[5,13]
Other Spurious
[4,5]
Ruggedness
[5]
EVM
PAE
I
CQ
I
AVG
I
PD
I
CTRL
Z
IN
2F
0
3F
0
, 4F
0
±
5 MHz offset
±
10 MHz offset
Second harmonic
Third and fourth harmonic
Between power modes
UMTS Band II
UMTS Band V, VIII
UMTS Band II
UMTS Band V, VIII
Load VSWR = 2.5:1
s34
s33, s44
T
ON
T
OFF
Load VSWR ≤ 5:1
No permanent damage or degradation
Notes:
1. Specifications at nominal operating conditions VIH = 1.8 V, VEN = 1.8 V, VBAT = 3.8 V, T
A
= 25 °C, RF ports at 50
Ω,
guaranteed over the full range of
operating frequency and guaranteed by production test unless indicated otherwise.
2. Specification is guaranteed using W-CDMA modulation RMC (12.2 kbps) in compliance with 3GPP Release 99.
3. RX band gain is specified relative to PA gain at 1950 MHz.
4. Specification is guaranteed over all power modes given in Table 3.
5. Specification is guaranteed by characterization.
6. Power added efficiency (PAE) includes total current consumption through all pins while PA is operating at maximum linear output power.
7. Calculated using three power modes (HP, MP, LP) with handset W-CDMA transmitter power distribution in GSMA DG.09 specification assuming 3
dB of post-PA loss.
8. Total supply current measured when the PA is disabled.
9. Specification applies to each VEN, VM0, and VM1 pin.
10. Interferer is CW at a relative power level of -40 dBc and offset from the W-CDMA modulated carrier.
11. Measured at CPLO pin.
12. Power variation measured at the RFO pin across 8 phase angles while power at CPLO pin is held constant.
13. Specified from the start of the PA enable transition to when the output power is within
±1
dB of final value.
14. Specification is guaranteed by characterization at P
MAX
.
15. Phase change should be measured at the center channel at each switch point and compensated in the baseband.
3
Application Information
VBAT
4.7 µF
0603
Low current <10µA
Pin 1 can be directly
connected to VBAT
VBAT
RF IN
VM1
VM0
VEN
1
2
3
4
5
VBAT
RFI
VM1
VM0
VEN
VBAT
RFO
10
9
8
7
6
CPLO
10 pF
0402
RF OUT
CPLI
AJAV-5601
CPLI
GND
CPLO
GND Paddle
Figure 1. Typical Single-Band Application Circuit
The AJAV-5601 is a complete, high-performance 3G Band
I power amplifier (PA) implemented in a standard CMOS
process. The AJAV-5601 delivers low current and inte-
grates TX filtering that produces the best noise in the in-
dustry. Only a single RF bypass capacitor is required, en-
abling a very low bill-of-materials (BOM). The AJAV-5601 is
fully compliant with W-CDMA, HSPA and HSPA+ standards
through 3GPP Release 7 and supports Power Class 3 and 4.
Figure 1 shows the typical application circuit. The AJAV-
5601 supports three power modes controlled by a stan-
dard CMOS interface enabling a direct connection to the
baseband with no level shifters. The VEN, VM0 and VM1
power control pins are high impedance with logic levels
defined in Table 2.
The AJAV-5601 may be powered by a single direct con-
nection to the battery, or controlled with an external DC-
DC converter. All power supply current flows through pin
10. Pin 1 is a low current input that can be directly con-
nected to VBAT or any other high level signal. No external
switches, isolation inductors, or bypass capacitors are re-
quired on Pin 1.
Standard RF practice should be followed for the PCB layout
of the RF traces for pins 2, 6, 8, and 9. Multiple vias should
be placed underneath the GND paddle to create a low re-
sistance path to ground and to ensure good heat conduc-
tion. Refer to Application Note 5565, (AV02-4080EN)
AJAV-
5xxx PCB Guidelines,
for additional information.
The AJAV-5601 features an integrated directional coupler
that can be daisy chained through the CPLI and CPLO
ports. For best performance, at least one port should see
a 50
Ω
path to GND. The CPLI port accepts an RF input or
can be terminated. The CPLO port provides the coupled
RF output that can be passed to the RF detector, termi-
nated or passed to the next PA in the daisy chain.
The AJAV-5601 includes integrated TX filtering that en-
sures excellent receiver sensitivity. As the RF signal passes
through the PA, the unwanted out-of-band noise pro-
duced by the transceiver is filtered out. Furthermore, the
thermal noise at the PA output is greatly reduced below
the level of a conventional GaAs PA. The resulting signal
at the output of the AJAV-5601 is spectrally very clean, en-
suring the best receiver sensitivity and producing minimal
interference to other radios in the system.
The AJAV-5601 integrates the RF Front-End Control Inter-
face (RFFE) version 1.1 from the MIPI Alliance. This option-
al interface is available for advanced features including
power control. For additional information on using the
MIPI interface, please contact your Avago support.
4
Top View (x-ray)
1
2
3
4
5
epad
10
9
8
7
6
Pin #
1
2
3
4
5
6
7
8
9
10
epad
Name
VBAT
RFI
VM1
VM0
VEN
CPLO
GND
CPLI
RFO
VBAT
GND
Description
DC Supply Voltage
RF Input
Mode Control
Mode Control
PA Enable
Coupler Output
Ground
Coupler Input
RF Output
DC Supply Voltage
Ground
TOP BRAND
J5601
YWWXX
Figure 2. Pin Descriptions
RFAT
TOP BRAND
J5601
YWWXX
RFAT
Laser dot
Pin 1 indicator:
Manufacturing part number: J5601
YWWXX
Trace code:
Y - Year
WW - Work week
XX - Lot number
Manufacturing information: RFAT
Pin 1
3. Package
Figure
indicator:
Marking
Laser dot
Manufacturing part number: J5601
YWWXX
Trace code:
Y - Year
WW - Work week
XX - Lot number
Manufacturing information: RFAT
5
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