Differential Clock Buffer/Driver DDR400- and DDR333-Compliant
Features
• Supports 333 MHz and 400-MHz DDR SDRAM
• 60- 200 MHz operating frequency
• Phase-locked loop (PLL) clock distribution for double
data rate synchronous DRAM applications
• Distributes one clock input to six differential outputs
• External feedback pin FBIN is used to synchronize
output to clock input
• Conforms to DDRI specification
• Spread Aware™ for electromagnetic interference (EMI)
reduction
• 28-pin SSOP package
Description
This PLL clock buffer is designed for 2.5-V
DD
and 2.5-AV
DD
operation and differential output levels.
This device is a zero delay buffer that distributes a clock input
CLKIN to six differential pairs of clock outputs (CLKT[0:5],
CLKC[0:5]) and one feedback clock output FBOUT. The clock
outputs are controlled by the input clock CLKIN and the
feedback clock FBIN.
The two-line serial bus can set each output clock pair
(CLKT[0:5], CLKC[0:5]) to the Hi-Z state. When AV
DD
is
grounded, the PLL is turned off and bypassed for test
purposes.
The PLL in this device uses the input clock CLKIN and the
feedback clock FBIN to provide high-performance, low-skew,
low–jitter output differential clocks.
Block Diagram
Pin Configuration
10
SCLK
SDATA
Serial
Interface
Logic
CLKT2
CLKC2
CLKT3
CLKC3
CLKIN
NC
AVDD
AGND
VDD
CLKT2
CLKC2
CY28352
CLKT0
CLKC0
CLKT1
CLKC1
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
SCLK
CLKIN
PLL
FBIN
CLKT4
CLKC4
CLKT5
CLKC5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
CLKC5
CLKT5
CLKC4
CLKT4
VDD
SDATA
NC
FBIN
FBOUT
NC
CLKT3
CLKC3
GND
AVDD
FBOUT
28 pin SSOP
Rev 1.0, November 21, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555
Fax:(408) 855-0550
Page 1 of 7
www.SpectraLinear.com
CY28352
Pin Description
[1]
Pin Number Pin Name
8
CLKIN
20
FBIN
I/O
I
I
O
O
O
I
I/O
Pin Description
Complementary Clock Input.
Feedback Clock Input.
Connect to FBOUT for accessing the
PLL.
Clock Outputs
Clock Outputs
Feedback Clock Output.
Connect to FBIN for normal operation.
A bypass delay capacitor at this output will control Input
Reference/Output Clocks phase relationships.
Serial Clock Input.
Clocks data at SDATA into the internal
register.
Serial Data Input.
Input data is clocked to the internal register to
enable/disable individual outputs. This provides flexibility in
power management.
2.5V Power Supply for Logic
2.5V Power Supply for PLL
Ground
Analog Ground for PLL
Not Connected
Output
Electrical
Characteristics
Input
Input
Differential Outputs
2,4,13,17,24,
CLKT(0:5)
26
1,5,14,16,25,
CLKC(0:5)
27
19
7
22
3,12,23
10
6,15,28
11
9, 18, 21
FBOUT
SCLK
SDATA
VDD
AVDD
GND
AGND
NC
Data Input for the two line
serial bus
Data Input and Output for
the two line serial bus
2.5V Nominal
2.5V Nominal
Zero Delay Buffer
When used as a zero delay buffer the CY28352 will likely be
in a nested clock tree application. For these applications the
CY28352 offers a clock input as a PLL reference. The
CY28352 can then lock onto the reference and translate with
near zero delay to low-skew outputs. For normal operation, the
external feedback input, FBIN, is connected to the feedback
output, FBOUT. By connecting the feedback output to the
feedback input the propagation delay through the device is
eliminated. The PLL works to align the output edge with the
input reference edge thus producing a near zero delay. The
reference frequency affects the static phase offset of the PLL
and thus the relative delay between the inputs and outputs.
When V
DDA
is strapped LOW, the PLL is turned off and
bypassed for test purposes.
Power Management
The individual output enable/disable control of the CY28352
allows the user to implement unique power management
schemes into the design. Outputs are three-stated when
disabled through the two-line interface as individual bits are
set low in Byte0 and Byte1 registers. The feedback output
FBOUT cannot be disabled via two line serial bus. The
enabling and disabling of individual outputs is done in such a
manner as to eliminate the possibility of partial “runt” clocks.
Function Table
Inputs
VDDA
GND
GND
2.5V
2.5V
2.5V
CLKIN
L
H
L
H
<20 MHz
CLKT(0:5)
[2]
L
H
L
H
Hi-Z
Outputs
CLKC(0:5)
[2]
H
L
H
L
Hi-Z
FBOUT
L
H
L
H
Hi-Z
PLL
BYPASSED/OFF
BYPASSED/OFF
On
On
Off
Notes:
1. A bypass capacitor (0.1μF) should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins, their
high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
2. Each output pair can be three-stated via the two-line serial interface.
Rev 1.0, November 21, 2006
Page 2 of 7
CY28352
Serial Control Registers
Following the acknowledge of the Address Byte, two additional
Storage Temperature: ................................ –65°C to + 150°C
Operating Temperature:.................................... 0°C to +70°C
Maximum Power Supply: ................................................ 3.5V
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, V
IN
and V
OUT
should be constrained to
the range:
V
SS
< (V
IN
or V
OUT
) < V
DD
.
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
or V
DD
).
DC Parameters
V
DDA
= V
DDQ
= 2.5V ± 5%, T
A
= 0°C to +70°C
[4]
Parameter
VIL
VIH
VIL
VIH
IIN
IOL
IOH
VOL
VOH
VOUT
VOC
IOZ
IDDQ
IDSTAT
IDD
Cin
Description
Input Low Voltage
Input High Voltage
Input Voltage Low
Input Voltage High
Input Current
Output Low Current
Condition
SDATA, SCLK
SDATA, SCLK
CLKIN, FBIN
CLKIN, FBIN
V
IN
= 0V or V
IN
= V
DDQ
, CLKIN,
FBIN
V
DDQ
= 2.375V, V
OUT
= 1.2V
Min.
2.2
0.4
2.1
–10
26
–18
35
–32
0.6
V
DDQ
– 0.4
(V
DDQ
/2) + 0.2
10
300
1
9
4
12
6
10
Typ.
Max.
1.0
Unit
V
V
V
V
µA
mA
mA
V
V
V
V
µA
mA
mA
mA
pF
Output High Current
V
DDQ
= 2.375V, V
OUT
= 1V
Output Low Voltage
V
DDQ
= 2.375V, I
OL
= 12 mA
Output High Voltage
V
DDQ
= 2.375V, I
OH
= –12 mA
1.7
Output Voltage Swing
[5]
1.1
[6]
Output Crossing Voltage
(V
DDQ
/2) – 0.2
High-Impedance Output
–10
V
O
= GND or V
O
= V
DDQ
Current
All V
DDQ
and V
DDI
,
Dynamic Supply Current
[7]
FO = 170 MHz
Static Supply Current
PLL Supply Current
V
DDA
only
Input Pin Capacitance
[7, 9]
V
DDQ
/2
235
AC Parameters
V
DD
= V
DDQ
= 2.5V ± 5%, T
A
= 0°C to +70°C
Parameter
fCLK
tDC
tlock
Tr / Tf
tpZL, tpZH
tpLZ, tpHZ
tCCJ
tjit(h-per)
Description
Operating Clock Frequency
Input Clock Duty Cycle
Maximum PLL lock Time
Output Clocks Slew Rate
Output Enable Time
[10]
(all outputs)
Output Disable Time
[10]
(all outputs)
Cycle-to-Cycle Jitter
[12]
Half-period jitter
[12]
Condition
Min.
60
40
1
Typ.
20% to 80% of V
OD
Max.
200
60
100
2.5
Unit
MHz
%
μs
V/ns
ns
ns
3
3
f > 66 MHz
f > 66 MHz
–100
–100
100
100
ps
ps
Notes:
3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4. Unused inputs must be held HIGH or LOW to prevent them from floating.
5. For load conditions, see
Figure 7.
6. The value of V
OC
is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120Ω resistor. See
Figure 7.
7. All outputs switching loaded with 16 pF in 60Ω environment. SeeFigure
7.
8. Parameters are guaranteed by design and characterization. Not 100% tested in production.
9. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 33.3 kHz, with a down
spread of –0.5%.
10. Refers to transition of non-inverting output.
11. All differential input and output terminals are terminated with 120Ω/16 pF as shown in
Figure 7.
12. Period Jitter and Half-Period Jitter specifications are separate, and must be met independently of each other.
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