K4T1G164QE-HIE60 datasheet, PDF

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K4T1G164QE-HIE60: DescriptionDDR DRAM, 64MX16, 0.45ns, CMOS, PBGA84, HALOGEN FREE AND ROHS COMPLIANT, FBGA-84; Categorystorage storage; File Size822KB，42 Pages; ManufacturerSAMSUNG; Websitehttp://www.samsung.com/Products/Semiconductor/

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K4T1G164QE-HIE60 Overview

DDR DRAM, 64MX16, 0.45ns, CMOS, PBGA84, HALOGEN FREE AND ROHS COMPLIANT, FBGA-84

K4T1G164QE-HIE60 Parametric

Parameter Name	Attribute value
Maker	SAMSUNG
Parts packaging code	BGA
package instruction	TFBGA,
Contacts	84
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	MULTI BANK PAGE BURST
Maximum access time	0.45 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B84
length	12.5 mm
memory density	1073741824 bit
Memory IC Type	DDR DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	84
word count	67108864 words
character code	64000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	95 °C
Minimum operating temperature	-40 °C
organize	64MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Certification status	Not Qualified
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
width	7.5 mm

K4T1G164QE-HIE60 Preview

K4T1G164QE

Industrial

DDR2 SDRAM

1Gb E-die DDR2 SDRAM Specification

84FBGA with Lead-Free & Halogen-Free

(RoHS compliant)

INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,

AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE

CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-

WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-

OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT

GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar

applications where Product failure could result in loss of life or personal or physical harm, or any military or

defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

1 of 45

Rev. 1.2 December 2008

K4T1G164QE

Industrial

DDR2 SDRAM

Table of Contents

1.0 Ordering Information ................................................................................................................... 4

2.0 Key Features ................................................................................................................................ 4

3.0 Package Pinout/Mechanical Dimension & Addressing ............................................................ 5

3.1 x16 package pinout (Top View) : 84ball FBGA Package

.................................................................... 5

.................................................................................................... 6

4.0 Input/Output Functional Description ......................................................................................... 7

5.0 DDR2 SDRAM Addressing .......................................................................................................... 8

6.0 Absolute Maximum DC Ratings .................................................................................................. 9

7.0 AC & DC Operating Conditions .................................................................................................. 9

7.1 Recommended DC Operating Conditions (SSTL - 1.8)

...................................................................... 9

7.2 Operating Temperature Condition

............................................................................................... 10

7.3 Input DC Logic Level

.................................................................................................................. 10

7.4 Input AC Logic Level

.................................................................................................................. 10

7.5 AC Input Test Conditions

........................................................................................................... 10

7.6 Differential input AC logic Level

.................................................................................................. 11

3.2 FBGA Package Dimension (x16)

................................................................................................ 11

8.0 ODT DC electrical characteristics ............................................................................................ 11

9.0 OCD default characteristics ...................................................................................................... 12

10.0 IDD Specification Parameters and Test Conditions ............................................................. 13

11.0 DDR2 SDRAM IDD Spec Table ................................................................................................ 15

12.0 Input/Output capacitance ........................................................................................................ 16

13.0 Electrical Characteristics & AC Timing for DDR2-800/667 ................................................... 16

13.1 Refresh Parameters by Device Density

..................................................................................... 16

13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin

........................................... 16

13.3 Timing Parameters by Speed Grade

.......................................................................................... 17

14.0 General notes, which may apply for all AC parameters ....................................................... 19

15.0 Specific Notes for dedicated AC parameters ........................................................................21

7.7 Differential AC output parameters

2 of 45

Rev. 1.2 December 2008

K4T1G164QE

Industrial

DDR2 SDRAM

Year

2008

- Initial Release

- Deleted a test condition of current spec on page 15.

- Updated AC/DC operating condition with the JEDEC update(JESD79-2E)

History

Revision History

Revision

1.0

1.1

1.2

Month

September

December

3 of 45

Rev. 1.2 December 2008

K4T1G164QE

1.0 Ordering Information

Org.

64Mx16

DDR2-800 6-6-6

K4T1G164QE-HI(P)F7

DDR2-667 5-5-5

K4T1G164QE-HI(P)E6

Industrial

DDR2 SDRAM

Package

84 FBGA

Note :

1. Speed bin is in order of CL-tRCD-tRP.

2. RoHS Compliant.

3. “H” of Part number(12th digit) stands for Lead-Free, Halogen-Free, and RoHS compliant products.

4. “I” of Part number(13th digit) stands normal, and “P” stands for Low power products.

2.0 Key Features

Speed

CAS Latency

tRCD(min)

tRP(min)

tRC(min)

DDR2-800 5-5-5

12.5

57.5

DDR2-800 6-6-6

DDR2-667 5-5-5

Units

tCK

• JEDEC standard V

= 1.8V ± 0.1V Power Supply

• V

DDQ

= 1.8V ± 0.1V

• 333MHz f

for 667Mb/sec/pin, 400MHz f

for 800Mb/sec/

• 8 Banks

• Posted CAS

• Programmable CAS Latency: 3, 4, 5, 6

• Programmable Additive Latenc y: 0, 1, 2, 3, 4, 5

• Write Latency(WL) = Read Latency(RL) -1

• Burst Length: 4 , 8(Interleave/nibble sequential)

• Programmable Sequential / Interleave Burst Mode

• Bi-directional Differential Data-Strobe (Single-ended data-

strobe is an optional feature)

• Off-Chip Driver(OCD) Impedance Adjustment

• On Die Termination

• Special Function Support

- 50ohm ODT

- High Temperature Self-Refresh rate enable

•

Average Refresh Period 7.8us at -40°C < T

CASE

< 95

°C

• All of products are Lead-Free, Halogen-Free, and RoHS com-

pliant

The 1Gb DDR2 SDRAM is organized as a 8Mbit x 16 I/Os x 8

banks device. This synchronous device achieves high speed dou-

ble-data-rate transfer rates of up to 800Mb/sec/pin (DDR2-800) for

general applications.

The chip is designed to comply with the following key DDR2

SDRAM features such as posted CAS with additive latency, write

latency = read latency - 1, Off-Chip Driver(OCD) impedance

adjustment and On Die Termination.

All of the control and address inputs are synchronized with a pair

of externally supplied differential clocks. Inputs are latched at the

crosspoint of differential clocks (CK rising and CK falling). All I/Os

are synchronized with a pair of bidirectional strobes (DQS and

DQS) in a source synchronous fashion. The address bus is used

to convey row, column, and bank address information in a RAS/

CAS multiplexing style. For example, 1Gb(x16) device receive 13/

10/3 addressing.

The 1Gb DDR2 device operates with a single 1.8V ± 0.1V power

supply and 1.8V ± 0.1V V

DDQ

The 1Gb DDR2 device is available in 84ball FBGA(x16).

Note : The functionality described and the timing specifications included in

this data sheet are for the DLL Enabled mode of operation.

Note : This data sheet is an abstract of full DDR2 specification and does not cover the common features which are described in “DDR2 SDRAM Device

Operation & Timing Diagram”.

4 of 45

Rev. 1.2 December 2008

K4T1G164QE

3.0 Package Pinout/Mechanical Dimension & Addressing

Industrial

DDR2 SDRAM

3.1 x16 package pinout (Top View) : 84ball FBGA Package

DQ14

DDQ

DQ12

DQ6

DDQ

DQ4

DDL

BA2

SSQ

DQ9

SSQ

DQ1

SSQ

REF

CKE

BA0

A10/AP

A12

UDM

DDQ

DQ11

LDM

DDQ

DQ3

BA1

SSQ

UDQS

DDQ

DQ10

SSQ

LDQS

DDQ

DQ2

SSDL

RAS

CAS

A11

UDQS

SSQ

DQ8

SSQ

LDQS

SSQ

DQ0

SSQ

DDQ

DQ15

DDQ

DQ13

DDQ

DQ7

DDQ

DQ5

ODT

Note : V

DDL

and V

SSDL

are power and ground for the DLL. It is recommended that they be isolated on the device from V

DDQ

, V

, and V

SSQ

Ball Locations (x16)

Populated ball

Ball not populated

Top view

(See the balls through package)

5 of 45

Rev. 1.2 December 2008

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K4T1G164QE-HIE60 Related Products

	K4T1G164QE-HIE60	K4T1G164QE-HIPE6	K4T1G164QE-HIF70	K4T1G164QE-HPF70
Description	DDR DRAM, 64MX16, 0.45ns, CMOS, PBGA84, HALOGEN FREE AND ROHS COMPLIANT, FBGA-84	DDR DRAM, 64MX16, 0.45ns, CMOS, PBGA84, HALOGEN FREE AND ROHS COMPLIANT, FBGA-84	DDR DRAM, 64MX16, 0.4ns, CMOS, PBGA84, HALOGEN FREE AND ROHS COMPLIANT, FBGA-84	DDR DRAM, 64MX16, 0.4ns, CMOS, PBGA84, HALOGEN FREE AND ROHS COMPLIANT, FBGA-84
Maker	SAMSUNG	SAMSUNG	SAMSUNG	SAMSUNG
Parts packaging code	BGA	BGA	BGA	BGA
package instruction	TFBGA,	TFBGA,	TFBGA,	TFBGA,
Contacts	84	84	84	84
Reach Compliance Code	unknown	unknown	unknown	unknown
ECCN code	EAR99	EAR99	EAR99	EAR99
access mode	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST
Maximum access time	0.45 ns	0.45 ns	0.4 ns	0.4 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B84	R-PBGA-B84	R-PBGA-B84	R-PBGA-B84
length	12.5 mm	12.5 mm	12.5 mm	12.5 mm
memory density	1073741824 bit	1073741824 bit	1073741824 bit	1073741824 bit
Memory IC Type	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
memory width	16	16	16	16
Number of functions	1	1	1	1
Number of ports	1	1	1	1
Number of terminals	84	84	84	84
word count	67108864 words	67108864 words	67108864 words	67108864 words
character code	64000000	64000000	64000000	64000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	95 °C	95 °C	95 °C	95 °C
Minimum operating temperature	-40 °C	-40 °C	-40 °C	-40 °C
organize	64MX16	64MX16	64MX16	64MX16
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TFBGA	TFBGA	TFBGA	TFBGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm
self refresh	YES	YES	YES	YES
Maximum supply voltage (Vsup)	1.9 V	1.9 V	1.9 V	1.9 V
Minimum supply voltage (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V
Nominal supply voltage (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL
Terminal form	BALL	BALL	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	7.5 mm	7.5 mm	7.5 mm	7.5 mm

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