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DATA SHEET
MOS INTEGRATED CIRCUITS
µ
PD16663
240-OUTPUT LCD COLUMN (SEGMENT) DRIVER WITH BUILT-IN RAM
DESCRIPTION
The
µ
PD16663 is a column (segment) driver device with built-in RAM. It is capable of driving a full-dot LCD.
There are 240 outputs that, with the 240
×
160
×
4-bit built-in display RAM, enable a 16-gray scale display. The
sixteen gray scales can be selected arbitrarily from a 49-stage palette. When combined with the
µ
PD16667, this
device can drive displays of 240
×
160 to 480
×
320 dots.
FEATURES
• Built-in display RAM: 240
×
160
×
4 bits
• Logic voltage: 3.0 to 3.6 V
• Duty cycle: 1/160
• Number of outputs: 240
• Gray scales: 16 (selectable from a palette of 49)
• Memory management: Packed pixel
• Compatible with 8-bit/16-bit data buses
ORDERING INFORMATION
Part number
Package
TCP (TAB)
2-side standard TCP
µ
PD16663N-×××
5
µ
PD16663N-051
Remark
The TCP's external shape is customized. To order the required shape, please contact
an NEC salesperson.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
Date Published
Printed in Japan
S13392EJ1V0DS00 (1st edition)
December 1999 NS CP(K)
The mark
5
shows major revised points.
©
1998, 1999
µ
PD16663
1. PIN FUNCTIONS
Classification
CPU Interface
Pin name
D
0
to D
15
A
0
to A
1
6
/CS
3.3 V
/OE
/WE
/UBE
RDY
Control signals
PL0
PL1
DIR
MS
BMODE
3.3 V
/REFRH
TEST
/RESET
/DOFF
OSC1
OSC2
STB
/FRM
5.0 V
PULSE
L1
L2
/DOUT
LCD drive
Power supply
Y
1
to Y
240
GND
V
CC1
V
CC2
V
0
V
1
V
2
Note
I/O
I/O
I
I
I
I
I
O
I
I
I
I
I
I/O
I
I
I
-
-
I/O
I/O
I/O
I/O
I/O
O
O
-
-
-
-
-
-
Data bus : 16 bits
Address bus : 17 bits
Chip select
Read signal
Write signal
Upper byte enable
Function
Ready signal issued to CPU ("H" sets ready status)
Specifies the LSI placement position (No. 0 to 3)
Specifies the LSI placement position (No. 0 to 3)
Specifies the direction of the LCD panel placement
Selects between master/slave ("H" sets master mode)
Selects the data bus bit ("H" sets 8 bits, "L" sets 16 bits)
Self-diagnostics reset pin (Wired-OR connection)
Test pin ("H" sets test mode, pull-down resistor is built-in)
Reset signal
Display OFF input signal
For external resistor for oscillator
For external resistor for oscillator
Column driving signal (MS pin "H" sets output, MS pin "L" sets input)
Frame signal (MS pin "H" sets output, MS pin "L" sets input)
25-gray-scale pulse modulation clock
Row driver driving level select signal (line 1)
Row driver driving level select signal (line 2)
Display OFF output signal
LCD drive output
Ground (× 2 for 5 V,
×
3 for 3.3 V)
5-V power supply
3.3-V power supply
LCD drive analog power supply
LCD drive analog power supply
LCD drive analog power supply
Note
3.3-V pins : D
0
to D
15
, A
0
to A
16
, /CS, /OE, /WE, /UBE, RDY, BMODE, PL0, PL1, DIR, OSC1, OSC2, /RESET,
/DOFF, TEST, MS
5-V pins
:STB, /FRM, L1, L2, /DOUT, PULSE
Remark
N.C. = Non-connection
Data Sheet S13392EJ1V0DS00
3
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