Standard Products
UT54LVDM055LV Dual
Driver and Receiver
Data Sheet
September, 2015
The most important thing we build is trust
FEATURES
Two drivers and two receivers with individual enables
>400.0 Mbps (200 MHz) switching rates
+340mV differential signaling
3.3 V power supply
TTL compatible inputs
INTRODUCTION
The UT54LVDM055LV Dual Driver/Dual Receiver is designed
for applications requiring ultra low power dissipation and high data
rates. The device is designed to support data rates in excess of 400.0
Mbps (200 MHz) utilizing Low Voltage Differential Signaling
(LVDS) technology.
The UT54LVDM055LV Driver accepts low voltage TTL input
levels and translates them to low voltage (350mV) differential
output signals. In addition, the driver supports a three-state function
that may be used to disable the output stage, disabling the load
current, and thus dropping the device to a low idle power state.
The UT54LVDM055LV Receiver accepts low voltage (350mV)
differential input signals and translates them to 3V CMOS output
levels. The receiver supports a three-state function that may be used
to multiplex outputs. The receiver also supports OPEN, shorted
and terminated (35
)
input fail-safe. Receiver output will be
HIGH for all fail-safe conditions.
All pins have Cold Spare buffers. These buffers will be high
impedance when V
DD
is tied to V
SS
.
10mA
LVDS output drivers
TTL compatible outputs
Cold spare all pins
Ultra low power CMOS technology
Operational environment; total dose irradiation testing to MIL-
STD-883 Method 1019
- Total-dose: 300 krad(Si)
- Latchup immune (LET > 100 MeV-cm
2
/mg)
Packaging options:
- 18-lead flatpack (0.8 grams)
Standard Microcircuit Drawing 5962-06202
- QML Q and V compliant part
Compatible with TIA/EIA-899
R
IN1+
R
IN1-
REN1
R
IN2+
R
IN2-
REN2
D
OUT2+
D
OUT2-
DEN2
D
OUT1+
D
OUT1-
DEN1
+
R1
-
R
OUT1
+
R2
-
R
OUT2
D2
D
IN2
D1
D
IN1
Figure 1. UT54LVDM055LV Dual Driver and Receiver Block Diagram
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APPLICATIONS INFORMATION
The UT54LVDM055LV provides two drivers and two receivers
in the same package. Each driver and each receiver has a dedi-
cated output enable pin. This allows maximum flexibility for the
device.
The intended application of these devices and signaling tech-
nique is for both point-to-point (single termination) and multi-
point (double termination) data transmissions over controlled
impedance media. The transmission media may be printed-circuit
board traces, backplanes, or cables. (Note: The ultimate rate and
distance of data transfer is dependent upon the attenuation char-
acteristics of the media, the noise coupling to the environment,
and other application specific characteristics.)
The UT54LVMS055LV differential line driver is a balanced
current source design. A current mode driver, has a high output
impedance and supplies a constant current for a range of loads (a
voltage mode driver on the other hand supplies a constant voltage
for a range of loads). Current is switched through the load in one
direction to produce a logic state and in the other direction to pro-
duce the other logic state. The current mode
requires
that a resis-
tive termination be employed to terminate the signal and to
complete the loop as shown in Figure 3. AC or unterminated con-
figurations are not allowed. The 10mA loop current will develop
a differential voltage of 350mV across the 35 termination resis-
tor which the receiver detects with a 250mV minimum differen-
tial noise margin neglecting resistive line losses (driven signal
minus receiver threshold (350mV - 100mV = 250mV)). The sig-
nal is centered around +1.2V (Driver Offset, VOS) with respect
to ground as shown in Figure 4.
Note:
The steady-state voltage
(VSS) peak-to-peak swing is twice the differential voltage
(VOD) and is typically 700mV.
The UT54LVDM055LV receiver’s are capable of
detecting signals as low as 100mV, over a +/- 1V common-mode
range centered around +1.2V. Both receiver input
pins should honor their specified operating input voltage range of
0V to +2.4V (measured from each pin to ground).
The receiver is connected to the driver through a balanced media
which may be a standard twisted pair cable, a parallel pair cable,
or simply PCB traces. The termination resistor converts the cur-
rent sourced by the driver into voltages that are detected by the
receiver. Other configurations are possible such as a multi-
receiver configuration, but the effects of a mid-stream connec-
tor(s), cable stub(s), and other impedance discontinuities, as well
as ground shifting, noise margin limits, and total termination
loading must be taken into account.
ENABLE
DATA
INPUT
LVDS Driver
RT 35
LVDS Receiver
+
-
DATA
OUTPUT
Figure 3. Point-to-Point Application
Receiver Fail-Safe
The UT54LVDM055LV receiver is a high gain, high speed device
that amplifies a small differential signal (20mV) to TTL logic
levels. Due to the high gain and tight threshold of the receiver, care
should be taken to prevent noise from appearing as a valid signal.
The receiver’s internal fail-safe circuitry is designed to source/sink
a small amount of current, providing fail-safe protection (a stable
known state of HIGH output voltage) for floating, terminated or
shorted receiver inputs.
Open Input Pins.
The UT54LVDM055LV is a dual receiver
device, and if an application requires only 1 receiver, the unused
channel inputs should be left OPEN. Do not tie unused receiver
inputs to ground or any other voltages. The input is biased by
internal high value pull up and pull down resistors to set the output
to a HIGH state. This internal circuitry will guarantee a HIGH,
stable output state for open inputs.
Terminated Input.
If the driver is disconnected (cable
unplugged), or if the driver is in a three-state or power-off
condition, the receiver output will again be in a HIGH state, even
with the end of cable 35 termination resistor across the input pins.
The unplugged cable can become a floating antenna which can
pick up noise. If the cable picks up more than 10mV of differential
noise, the receiver may see the noise as a valid signal and switch.
To insure that any noise is seen as common-mode and not
differential, a balanced interconnect should be used. Twisted pair
cable offers better balance than flat ribbon cable.
Shorted Inputs.
If a fault condition occurs that shorts the receiver
inputs together, thus resulting in a 0V differential input voltage,
the receiver output remains in a HIGH state. Shorted input fail-safe
is not supported across the common-mode range of the device (V
SS
to 2.4V). It is only supported with inputs shorted and no external
common-mode voltage applied.
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OPERATIONAL ENVIRONMENT
PARAMETER
Total Ionizing Dose (TID)
Single Event Latchup (SEL)
LIMIT
1.0E6
>100
UNITS
rad(Si)
MeV-cm
2
/mg
ABSOLUTE MAXIMUM RATINGS
1
(Referenced to V
SS
)
SYMBOL
V
DD
V
I/O
PARAMETER
DC supply voltage
Voltage on any pin during operation
Voltage on any pin during cold spare
T
STG
P
D
T
J
JC
I
I
Storage temperature
Maximum power dissipation
Maximum junction temperature
2
Thermal resistance, junction-to-case
3
DC input current
LIMITS
-0.3 to 4.0V
-0.3 to (V
DD
+ 0.3V)
-.3 to 4.0V
-65 to +150C
1.25 W
+150C
10C/W
±
10mA
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175C during burn-in and life test.
3. Test per MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
T
C
V
IN
PARAMETER
Positive supply voltage
Case temperature range
DC input voltage, receiver inputs
DC input voltage, logic inputs
LIMITS
3.0 to 3.6V
-55 to +125C
2.4V
0 to V
DD
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DC ELECTRICAL CHARACTERISTICS DRIVER *
1, 2,4
(V
DD
= 3.3V + 0.3V; -55C < T
C
< +125C); Unless otherwise noted, Tc is per the temperature range ordered
SYMBOL
V
IH
V
IL
V
OL
V
OH
I
IN
I
CS
V
OD1
V
OD1
V
OS
V
OS
V
CL
I
OS2, 3
PARAMETER
High-level input voltage
Low-level input voltage
Low-level output voltage
High-level output voltage
Input leakage current
Cold Spare Leakage Current
Differential Output Voltage
Change in Magnitude of V
OD
for
Complementary Output States
Offset Voltage
(TTL)
(TTL)
R
L
= 35
R
L
= 35
V
IN
= V
DD
or GND, V
DD
= 3.6V
V
IN
=3.6V, V
DD
=V
SS
R
L
= 35
(figure 5)
R
L
= 35
(figure 5)
R
L
= 35, V
OS
=
--------------------------------
R
L
= 35
(figure 5)
VOH + VOL
-
2
CONDITION
MIN
2.0
MAX
UNIT
V
0.8
0.855
1.750
-5
-10
250
+5
+10
400
35
1.055
1.550
V
V
V
A
mV
mV
V
Change in Magnitude of V
OS
for
Complementary Output States
Input clamp voltage
Output Short Circuit Current
35
-1.5
40
mV
V
mA
I
CL
= +18mA
V
IN
= V
DD
, V
OUT+
= 0V or
V
IN
= GND, V
OUT-
= 0V, D
EN
= V
DD
D
EN
= 0.8V
V
OUT
= 0V or V
DD,
V
DD
= 3.6V
R
L
= 35 all channels
R
EN
= D
EN
= V
DD
V
IN
= V
DD
or V
SS
(all inputs)
D
IN
= V
DD
or V
SS
R
EN
= D
EN
= V
SS
-5
I
OZ
I
CCL4
Output Three-State Current
+5
Loaded supply current, drivers and
receivers enabled
mA
40.0
I
CCZ4
Loaded supply current, drivers and
receivers disabled
mA
15.0
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25
o
C per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except differential voltages.
2. Output short circuit current (I
OS
) is specified as magnitude only, minus sign indicates direction only.
3. Guaranteed by characterization
4. Receivers are included for parameters I
CCL
and I
CCZ
.
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