NAND98R3M0AZBA5E datasheet, PDF

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NAND98R3M0AZBA5E: DescriptionMemory Circuit, Flash+SDRAM, PBGA149; Categorystorage storage; File Size725KB，33 Pages; ManufacturerMicron Technology; Websitehttp://www.mdtic.com.tw/; Environmental Compliance

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NAND98R3M0AZBA5E Overview

Memory Circuit, Flash+SDRAM, PBGA149

NAND98R3M0AZBA5E Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Micron Technology
package instruction	FBGA, BGA149,12X16,32
Reach Compliance Code	compliant
JESD-30 code	R-PBGA-B149
Memory IC Type	MEMORY CIRCUIT
Mixed memory types	FLASH+SDRAM
Number of terminals	149
Maximum operating temperature	85 °C
Minimum operating temperature	-30 °C
Package body material	PLASTIC/EPOXY
encapsulated code	FBGA
Encapsulate equivalent code	BGA149,12X16,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, FINE PITCH
power supply	1.8 V
Certification status	Not Qualified
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
Temperature level	OTHER
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM

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NANDxxxxMx

256/512-Mbit or 1-Gbit (x8/x16, 1.8/2.6 V, 528-byte page) NAND

flash and 256/512-Mbit (x16/x32, 1.8 V) LPSDRAM, MCP or PoP

Features

FBGA

Packages

– MCP (multichip package)

– PoP (package on package)

Device composition

– 1 die of 256 or 512 Mbits or 1 Gbit (x8/x16)

SLC small page NAND flash memory

– 1 die of 256 or 512 Mbits (x16 or x32)

SDR/DDR LPSDRAM

Supply voltages

– V

DDF

= 1.7 V to 1.95 V or 2.5 V to 3.6 V

– V

DDD

= V

DDQD

= 1.7 V to 1.95 V

Electronic signature

ECOPACK

packages

Temperature range: –30 to 85 °C

TFBGA107 10.5 × 13 × 1.2 mm (ZBB)

TFBGA149 10 × 13.5 × 1.2 mm (ZBA)

TFBGA137 10.5 × 13 × 1.2 mm (ZBC)

LFBGA137 10.5 × 13 × 1.4 mm (ZBC)

FBGA

TFBGA152 14 x 14 x 1.1 mm (ZPA)

Data integrity

– 100 000 program/erase cycles

– 10 years data retention

Flash memory

Single or double data rate LPSDRAM

NAND interface

– x8/x16 bus width

– Multiplexed address/data

Page size

– x8 device: (512 + 16 spare) bytes

– x16 device: (256 + 8 spare) words

Block size

– x8 device: (16K + 512 spare) bytes

– x16 device: (8K + 256 spare) words

Page read/program

– Random access: 12 µs (3 V), 15 µs (1.8 V)

– Sequential access: 30 ns (3 V), 50 ns

(1.8 V)

– Page program time: 200 µs (typ)

Copy back program mode

– Fast page copy without external buffering

Fast block erase

– Block erase time: 2 ms (typ)

– Status register

Interface: ×16 or ×32 bus width

Deep power-down mode

1.8 V LVCMOS interface

Quad internal banks controlled by BA0, BA1

Automatic and controlled precharge

Auto refresh and self refresh

– 8 192 refresh cycles/64 ms

– Programmable partial array self refresh

– Auto temperature compensated self refresh

Wrap sequence: sequential/interleave

Burst termination by Burst Stop command and

Precharge command

Device summary

NAND99W3M0 NAND98R4M2

NAND99W3M1 NAND99R3M1

NANDA9W3M1

NAND99R4M2

NAND98W3M1

NAND98R3M2

Table 1.

NANDxxxxMx

Rev 13

NAND88R3M0

NAND98R3M0

NAND98W3M0

NAND99R3M0

NAND99R3M2

NAND98R3M1

October 2008

1/32

www.numonyx.com

Contents

NANDxxxxMx

Contents

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.1

1.2

NAND flash memory component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

LPSDRAM component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

2.10

2.11

2.12

2.13

2.14

2.15

2.16

2.17

2.18

2.19

2.20

2.21

2.22

2.23

2.24

2.25

2.26

Flash memory inputs/outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . . 16

Flash memory inputs/outputs (I/O8-I/O15) . . . . . . . . . . . . . . . . . . . . . . . . 16

Flash memory Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . 16

Flash memory Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . 16

Flash memory Chip Enable (E

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Flash memory Read Enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Flash memory Write Enable (W

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Flash memory Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Flash memory Ready/Busy (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Flash memory V

DDF

supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Flash memory V

SSF

ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

LPSDRAM address inputs (A0-A12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

LPSDRAM bank select address inputs (BA0-BA1) . . . . . . . . . . . . . . . . . 18

LPSDRAM data inputs/outputs (DQ0-DQ15 and DQ16-DQ31) . . . . . . . . 18

LPSDRAM Chip Select (E

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

LPSDRAM Column Address Strobe (CAS) . . . . . . . . . . . . . . . . . . . . . . . 18

LPSDRAM Row Address Strobe (RAS) . . . . . . . . . . . . . . . . . . . . . . . . . . 18

LPSDRAM Write Enable (W

) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

LPSDRAM Clock Input (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

LPSDRAM Clock Enable (KE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Lower/Upper Data Read/Write Strobe input/output (LDQS, UDQS) . . . . 19

LPSDRAM data input/output mask pins (DQM0, DQM1, DQM2, DQM3) 19

LPSDRAM V

DDD

supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

LPSDRAM V

DDQD

supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

LPSDRAM V

SSD

ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

2/32

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