L-FW32207T100-DB datasheet, PDF

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L-FW32207T100-DB: DescriptionSerial I/O Controller, 2 Channel(s), 50MBps, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100; CategoryThe embedded processor and controller Microcontrollers and processors; File Size919KB，86 Pages; ManufacturerBroadcom; Environmental Compliance

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L-FW32207T100-DB Overview

Serial I/O Controller, 2 Channel(s), 50MBps, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100

L-FW32207T100-DB Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	Broadcom
package instruction	ROHS COMPLIANT, TQFP-100
Reach Compliance Code	compliant
Address bus width
boundary scan	NO
maximum clock frequency	24.578 MHz
letter of agreement	ASYNC, BIT
Maximum data transfer rate	50 MBps
External data bus width
JESD-30 code	S-PQFP-G100
JESD-609 code	e3
length	14 mm
low power mode	YES
Number of serial I/Os	2
Number of terminals	100
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Encapsulate equivalent code	QFP100,.63SQ,20
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	250
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage	3.6 V
Minimum supply voltage	3 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	14 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL

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Data Sheet, Rev. 1

October 2006

™

FW322 07 T100

1394a PCI PHY/Link Open Host Controller

1 Features

1394a-2000 OHCI link and PHY core function in a

single device:

— 100-pin TQFP package (also available in a lead-

free package; see ordering information on

page 86.)

— Single-chip link and PHY enable smaller, simpler,

more efficient motherboard and add-in card

designs

— Enables lower system costs

— Leverages proven 1394a-2000 PHY core design

— Demonstrated compatibility with current

Microsoft

Windows

drivers and common applications

— Demonstrated interoperability with existing, as well

as older, 1394 consumer electronics and periph-

erals products

— Feature-rich implementation for high performance

in common applications

— Supports low-power system designs (CMOS

implementation, power management features)

OHCI:

— Complies with the

1394 OHCI 1.1 Specification

— OHCI 1.0 backwards compatible—configurable via

EEPROM to operate in either OHCI 1.0 or

OHCI 1.1 mode

— Complies with

Microsoft Windows

logo program

system and device requirements

— Listed on

Windows

hardware compatibility list

http://testedproducts.windowsmarketplace.com/.

— Compatible with

Microsoft Windows

and

MacOS

operating systems

— 4 Kbyte isochronous transmit FIFO

— 2 Kbyte asynchronous transmit FIFO

— 4 Kbyte isochronous receive FIFO

— 2 Kbyte asynchronous receive FIFO

— Dedicated asynchronous and isochronous

descriptor-based DMA engines

— Eight isochronous transmit contexts

— Eight isochronous receive contexts

— Prefetches isochronous transmit data

— Supports posted write transactions

— Supports parallel processing of incoming physical

read and write requests

— Supports notification (via interrupt) of a failed

1394a-2000 PHY core:

— Compliant with

IEEE

1394a-2000,

Standard for a

High Performance Serial Bus

(Supplement)

— Provides two fully compliant cable ports, each

supporting 400 Mbits/s, 200 Mbits/s, and

100 Mbits/s traffic

— Supports extended BIAS_HANDSHAKE time for

enhanced interoperability with camcorders

— While unpowered and connected to the bus, will

not drive TPBIAS on a connected port even if

receiving incoming bias voltage on that port

— Does not require external filter capacitor for PLL

— Supports link-on as a part of the internal

PHY core-link interface

— 25 MHz crystal oscillator and internal PLL provide

a 50 MHz internal

link-layer controller clock as

well as

transmit/receive data at 100 Mbits/s,

200 Mbits/s, and 400 Mbits/s

— Interoperable across 1394 cable with 1394 phys-

ical layers (PHY core) using 5 V supplies

— Provides node power-class information signaling

for system power management

— Supports ack-accelerated arbitration and fly-by

concatenation

— Supports arbitrated short bus reset to improve

utilization of the bus

— Fully supports suspend/resume

— Supports connection debounce

— Supports multispeed packet concatenation

— Supports PHY pinging and remote PHY access

packets

— Reports cable power fail interrupt when voltage at

CPS pin falls below 7.5 V

— Provides separate cable bias and driver termina-

tion voltage supply for each port

Link:

— Cycle master and isochronous resource manager

capable

— Supports 1394a-2000 acceleration features

PCI:

— Revision 2.3 compliant

— 33 MHz/32-bit operation

— Programmable burst size thresholds for PCI data

transfer

— Supports optimized memory read line, memory

read multiple, and memory write invalidate burst

commands

— Supports

PCI Bus Power Management Interface

Specification

v.1.1

Note:

This device does not support D3cold wakeup,

CLKRUN protocol,

mini PCI

applications, and

CardBus applications. Use the FW322 06

120-pin TQFP device if one or more of these

features are needed.

FW322 07 T100

1394a PCI PHY/Link Open Host Controller

Data Sheet, Rev. 1

October 2006

Table of Contents

Contents

Page

Features .......................................................................................................................................................... 1

1.1 Other Features ....................................................................................................................................... 6

FW322 Functional Overview ........................................................................................................................... 6

FW322 Functional Description ........................................................................................................................ 7

3.1 PCI Core ................................................................................................................................................. 7

3.2 OHCI Data Transfer ................................................................................................................................ 8

3.3 OHCI Isochronous Data Transfer ........................................................................................................... 8

3.4 Isochronous Register Access ................................................................................................................. 9

3.5 OHCI Asynchronous Data Transfer ........................................................................................................ 9

3.6 Asynchronous Register Access .............................................................................................................. 9

3.7 Link Core .............................................................................................................................................. 11

3.8 PHY Core ............................................................................................................................................. 13

Pin Information .............................................................................................................................................. 15

Internal Registers .......................................................................................................................................... 21

5.1 PCI Configuration Registers ................................................................................................................. 21

5.2 Vendor ID Register ............................................................................................................................... 22

5.3 Device ID Register ................................................................................................................................ 22

5.4 PCI Command Register ........................................................................................................................ 23

5.5 PCI Status Register .............................................................................................................................. 24

5.6 Class Code and Revision ID Registers ................................................................................................ 25

5.7 Latency Timer and Cache Line Size Register ...................................................................................... 25

5.8 Header Type and BIST Register .......................................................................................................... 26

5.9 OHCI Base Address Register ............................................................................................................... 26

5.10 PCI Subsystem Identification Register ................................................................................................. 27

5.11 PCI Power Management Capabilities Pointer Register ........................................................................ 27

5.12 Interrupt Line and Pin Register ............................................................................................................. 28

5.13 MIN_GNT and MAX_LAT Register ....................................................................................................... 28

5.14 PCI OHCI Control Register ................................................................................................................... 29

5.15 Capability ID and Next Item Pointer Register ....................................................................................... 29

5.16 Power Management Capabilities Register ........................................................................................... 30

5.17 Power Management Control and Status Register ................................................................................ 31

5.18 Power Management CSR PCI-to-PCI Bridge Support Extensions ....................................................... 32

5.19 Power Management Data ..................................................................................................................... 32

5.20 OHCI Registers .................................................................................................................................... 33

5.21 OHCI Version Register ......................................................................................................................... 36

5.22 GUID ROM Register ............................................................................................................................. 37

5.23 Asynchronous Transmit Retries Register ............................................................................................. 37

5.24 CSR Data Register ............................................................................................................................... 38

5.25 CSR Compare Register ........................................................................................................................ 38

5.26 CSR Control Register ........................................................................................................................... 38

5.27 Configuration ROM Header Register .................................................................................................... 39

5.28 Bus Identification Register .................................................................................................................... 40

5.29 Bus Options Register ............................................................................................................................ 40

5.30 GUID High Register .............................................................................................................................. 41

5.31 GUID Low Register ............................................................................................................................... 41

5.32 Configuration ROM Mapping Register .................................................................................................. 42

5.33 Posted Write Address Low Register ..................................................................................................... 43

5.34 Posted Write Address High Register .................................................................................................... 43

5.35 Vendor ID Register ............................................................................................................................... 43

5.36 Host Controller Control Register ........................................................................................................... 44

5.37 SelfID Buffer Pointer Register .............................................................................................................. 46

Agere Systems Inc.

Data Sheet, Rev. 1

October 2006

FW322 07 T100

1394a PCI PHY/Link Open Host Controller

Table of Contents

(continued)

Contents

Page

5.38 SelfID Count Register ........................................................................................................................... 46

5.39 Isochronous Receive Multiple Channel Mask High (IRMultiChanMaskHi) Register ............................. 47

5.40 Isochronous Receive Multiple Channel Mask Low (IRMultiChanMaskLo) Register ............................. 47

5.41 Interrupt Event (IntEvent) Register ....................................................................................................... 48

5.42 Interrupt Mask (IntMask) Register ........................................................................................................ 50

5.43 Isochronous Transmit Interrupt Event (isoXmitIntMask) Register ........................................................ 52

5.44 Isochronous Transmit Interrupt Mask (isoXmitIntMask) Register ......................................................... 53

5.45 Isochronous Receive Interrupt Event (isoRecvIntEvent) Register ........................................................ 54

5.46 Isochronous Receive Interrupt Mask (isoRecvIntMask) Register ......................................................... 55

5.47 Fairness Control Register ..................................................................................................................... 55

5.48 Link Control Register ............................................................................................................................ 56

5.49 Node Identification Register .................................................................................................................. 57

5.50 PHY Core Layer Control Register ......................................................................................................... 58

5.51 Isochronous Cycle Timer Register ........................................................................................................ 58

5.52 Asynchronous Request Filter High Register ......................................................................................... 59

5.53 Asynchronous Request Filter Low Register .......................................................................................... 59

5.54 Physical Request Filter High Register .................................................................................................. 60

5.55 Physical Request Filter Low Register ................................................................................................... 60

5.56 Asynchronous Context Control Register ............................................................................................... 61

5.57 Asynchronous Context Command Pointer Register ............................................................................. 62

5.58 Isochronous Transmit Context Control (IT DMA ContextControl) Register .......................................... 63

5.59 Isochronous Transmit Context Command Pointer Register ................................................................. 64

5.60 Isochronous Receive Context Control (IR DMA ContextControl) Register ........................................... 65

5.61 Isochronous Receive Context Command Pointer Register .................................................................. 66

5.62 Isochronous Receive Context Match (IR DMA ContextMatch) Register .............................................. 67

5.63 FW322 Vendor-Specific Registers ........................................................................................................ 68

5.64 Isochronous DMA Control ..................................................................................................................... 68

5.65 Asynchronous DMA Control ................................................................................................................. 69

5.66 Link Options .......................................................................................................................................... 70

Internal Register Configuration ..................................................................................................................... 71

6.1 PHY Core Register Map ....................................................................................................................... 71

6.2 PHY Core Register Fields ..................................................................................................................... 72

Crystal Selection Considerations .................................................................................................................. 77

7.1 Load Capacitance ................................................................................................................................. 77

7.2 Adjustment to Crystal Loading .............................................................................................................. 77

7.3 Crystal/Board Layout ............................................................................................................................ 77

Serial EEPROM Interface ............................................................................................................................. 78

ac Characteristics of Serial EEPROM Interface Signals ............................................................................... 78

Solder Reflow and Handling .......................................................................................................................... 81

Absolute Maximum Voltage/Temperature Ratings ........................................................................................ 81

Electrical Characteristics ............................................................................................................................... 82

Timing Characteristics ................................................................................................................................... 84

Outline Diagrams .......................................................................................................................................... 85

14.1 100-Pin TQFP ....................................................................................................................................... 85

Ordering Information ..................................................................................................................................... 86

Agere Systems Inc.

FW322 07 T100

1394a PCI PHY/Link Open Host Controller

Data Sheet, Rev. 1

October 2006

Table of Contents

(continued)

Figure

Page

Figure 1. FW322 Conceptual Block Diagram........................................................................................................... 6

Figure 2. PCI Core Block Diagram...........................................................................................................................7

Figure 3. OHCI Core Block Diagram........................................................................................................................ 8

Figure 4. Link Core Block Diagram ........................................................................................................................ 11

Figure 5. The PHY Core Block Diagram ................................................................................................................12

Figure 6. Pin Assignments for the FW322 07 T100 ...............................................................................................15

Figure 7. Crystal Circuitry ......................................................................................................................................77

Figure 8. Bus Timing..............................................................................................................................................79

Figure 9. Write Cycle Timing..................................................................................................................................79

Figure 10. Data Validity ...........................................................................................................................................79

Figure 11. Start and Stop Definition ........................................................................................................................80

Figure 12. Output Acknowledge..............................................................................................................................80

Table

Page

Table 1. Pin Descriptions ....................................................................................................................................... 16

Table 2. Bit-Field Access Tag Description............................................................................................................. 21

Table 3. PCI Configuration Register Map............................................................................................................. 21

Table 4. PCI Command Register Description........................................................................................................ 23

Table 5. PCI Status Register ................................................................................................................................. 24

Table 6. Class Code and Revision ID Register Description .................................................................................. 25

Table 7. Latency Timer and Class Cache Line Size Register Description ........................................................... 25

Table 8. Header Type and BIST Register Description .......................................................................................... 26

Table 9. OHCI Base Address Register Description............................................................................................... 26

Table 10. PCI Subsystem Identification Register Description ............................................................................... 27

Table 11. Interrupt Line and Pin Register Description........................................................................................... 28

Table 12. MIN_GNT and MAX_LAT Register Description..................................................................................... 28

Table 13. PCI OHCI Control Register Description................................................................................................. 29

Table 14. Capability ID and Next Item Pointer Register Description ..................................................................... 29

Table 15. Power Management Capabilities Register Description ......................................................................... 30

Table 16. Power Management Control and Status Register Description .............................................................. 31

Table 17. Power Management Data Register Description .................................................................................... 32

Table 18. OHCI Register Map ............................................................................................................................... 33

Table 19. OHCI Version Register Description ....................................................................................................... 36

Table 20. GUID ROM Register Description ........................................................................................................... 37

Table 21. Asynchronous Transmit Retries Register Description ........................................................................... 37

Table 22. CSR Data Register Description ............................................................................................................. 38

Table 23. CSR Compare Register Description ...................................................................................................... 38

Table 24. CSR Control Register Description ........................................................................................................ 38

Table 25. Configuration ROM Header Register Description ................................................................................. 39

Table 26. Bus Identification Register Description .................................................................................................. 40

Table 27. Bus Options Register Description .......................................................................................................... 40

Table 28. GUID High Register Description ............................................................................................................ 41

Table 29. GUID Low Register Description ............................................................................................................. 41

Table 30. Configuration ROM Mapping Register Description ................................................................................ 42

Table 31. Posted Write Address Low Register Description ................................................................................... 43

Table 32. Posted Write Address High Register Description .................................................................................. 43

Table 33. Vendor ID Register Description ............................................................................................................. 43

Table 34. Host Controller Control Register Description ......................................................................................... 44

Table 35. SelfID Buffer Pointer Register Description ............................................................................................ 46

Agere Systems Inc.

Data Sheet, Rev. 1

October 2006

FW322 07 T100

1394a PCI PHY/Link Open Host Controller

Table of Contents

(continued)

Table

Page

Table 36. SelfID Count Register Description.......................................................................................................... 46

Table 37. Isochronous Receive Channel Mask High Register Description ............................................................ 47

Table 38. Isochronous Receive Channel Mask Low Register Description ............................................................. 47

Table 39. Interrupt Event Register Description....................................................................................................... 48

Table 40. Interrupt Mask Register Description ....................................................................................................... 50

Table 41. Isochronous Transmit Interrupt Event Register Description ................................................................... 52

Table 42. Isochronous Transmit Interrupt Event Description ................................................................................. 53

Table 43. Isochronous Receive Interrupt Event Description .................................................................................. 54

Table 44. Fairness Control Register Description.................................................................................................... 55

Table 45. Link Control Register Description .......................................................................................................... 56

Table 46. Node Identification Register Description ................................................................................................ 57

Table 47. PHY Core Layer Control Register Description ....................................................................................... 58

Table 48. Isochronous Cycle Timer Register Description ...................................................................................... 58

Table 49. Asynchronous Request Filter High Register Description........................................................................ 59

Table 50. Asynchronous Request Filter Low Register Description ........................................................................ 59

Table 51. Physical Request Filter High Register Description ................................................................................. 60

Table 52. Physical Request Filter Low Register Description.................................................................................. 60

Table 53. Asynchronous Context Control Register Description ............................................................................ 61

Table 54. Asynchronous Context Command Pointer Register Description ............................................................ 62

Table 55. Isochronous Transmit Context Control Register Description ................................................................. 63

Table 56. Isochronous Transmit Context Command Pointer Register Description ................................................ 64

Table 57. Isochronous Receive Context Control Register Description................................................................... 65

Table 58. Isochronous Receive Context Command Pointer Register Description ................................................. 66

Table 59. Isochronous Receive Context Match Register Description .................................................................... 67

Table 60. FW322 Vendor-Specific Registers Description ...................................................................................... 68

Table 61. Isochronous DMA Control Registers Description ................................................................................... 68

Table 62. Asynchronous DMA Control Registers Description ................................................................................ 69

Table 63. Link Options Register Description .......................................................................................................... 70

Table 64. PHY Core Register Map ......................................................................................................................... 71

Table 65. PHY Core Register Fields ...................................................................................................................... 72

Table 66. PHY Core Register Page 0: Port Status Page ....................................................................................... 74

Table 67. PHY Core Register Port Status Page Fields ......................................................................................... 75

Table 68. PHY Core Register Page 1: Vendor Identification Page ........................................................................ 76

Table 69. PHY Core Register Vendor Identification Page Fields ........................................................................... 76

Table 70. ac Characteristics of Serial EEPROM Interface Signals ........................................................................ 78

Table 71. Absolute Maximum Ratings.................................................................................................................... 81

Table 72. Analog Characteristics............................................................................................................................ 82

Table 73. Driver Characteristics ............................................................................................................................. 83

Table 74. Device Characteristics............................................................................................................................ 83

Table 75. Switching Characteristics ....................................................................................................................... 84

Table 76. Clock Characteristics.............................................................................................................................. 84

Agere Systems Inc.

L-FW32207T100-DB Related Products

	L-FW32207T100-DB	L-FW32207T100-DT
Description	Serial I/O Controller, 2 Channel(s), 50MBps, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100	Serial I/O Controller, 2 Channel(s), 50MBps, CMOS, PQFP100, ROHS COMPLIANT, TQFP-100
Is it Rohs certified?	conform to	conform to
Maker	Broadcom	Broadcom
package instruction	ROHS COMPLIANT, TQFP-100	ROHS COMPLIANT, TQFP-100
Reach Compliance Code	compliant	compliant
boundary scan	NO	NO
maximum clock frequency	24.578 MHz	24.578 MHz
letter of agreement	ASYNC, BIT	ASYNC, BIT
Maximum data transfer rate	50 MBps	50 MBps
JESD-30 code	S-PQFP-G100	S-PQFP-G100
JESD-609 code	e3	e3
length	14 mm	14 mm
low power mode	YES	YES
Number of serial I/Os	2	2
Number of terminals	100	100
Maximum operating temperature	70 °C	70 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFQFP	LFQFP
Encapsulate equivalent code	QFP100,.63SQ,20	QFP100,.63SQ,20
Package shape	SQUARE	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH
Peak Reflow Temperature (Celsius)	250	250
power supply	3.3 V	3.3 V
Certification status	Not Qualified	Not Qualified
Maximum seat height	1.6 mm	1.6 mm
Maximum supply voltage	3.6 V	3.6 V
Minimum supply voltage	3 V	3 V
Nominal supply voltage	3.3 V	3.3 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL
Terminal surface	Matte Tin (Sn)	Matte Tin (Sn)
Terminal form	GULL WING	GULL WING
Terminal pitch	0.5 mm	0.5 mm
Terminal location	QUAD	QUAD
Maximum time at peak reflow temperature	40	40
width	14 mm	14 mm
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL	SERIAL IO/COMMUNICATION CONTROLLER, SERIAL

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