DATA SHEET
µ
PD464318L, 464336L
4M-BIT Bi-CMOS SYNCHRONOUS FAST STATIC RAM
256K-WORD BY 18-BIT / 128K-WORD BY 36-BIT
HSTL INTERFACE
MOS INTEGRATED CIRCUIT
Description
The
µ
PD464318L is a 262,144 words by 18 bits, and the
µ
PD464336L is a 131,072 words by 36 bits synchronous
static RAM fabricated with advanced Bi-CMOS technology using N-channel memory cell.
This technology and unique peripheral circuits make the
µ
PD464318L and
µ
PD464336L a high-speed device. The
µ
PD464318L and
µ
PD464336L are suitable for applications which require high-speed, low voltage, high-density
memory and wide bit configuration, such as cache and buffer memory.
These are packaged in a 119-pin plastic BGA (Ball Grid Array).
Features
•
Fully synchronous operation
•
Fast clock access time : 2.6 ns / 200 MHz, 3.0 ns / 167 MHz, 3.5 ns / 154 MHz
•
Single Differential Single clock, Registered Input / Registered Output
•
Asynchronous output enable control : /G
•
Byte write control : /SBa (DQa1-9), /SBb (DQb1-9), /SBc (DQc1-9), /SBd (DQd1-9)
•
Common I/O using three-state outputs
•
Internally self-timed write cycle
•
Late write with 1 dead cycle between Read-Write
•
User-configurable outputs :
Controlled impedance outputs or push-pull outputs
•
Boundary scan (JTAG) IEEE 1149.1 compatible
•
3.3 V (Chip) / 1.5V (I/O) supply
Ordering Information
Part number
Access time
2.6 ns
3.0 ns
3.5 ns
2.6 ns
3.0 ns
3.5 ns
Clock frequency
200 MHz
167 MHz
154 MHz
200 MHz
167 MHz
154 MHz
Package
119-pin plastic BGA
µ
PD464318LS1-A5
µ
PD464318LS1-A6
µ
PD464318LS1-A65
µ
PD464336LS1-A5
µ
PD464336LS1-A6
µ
PD464336LS1-A65
The information in this document is subject to change without notice.
Document No. M12000EJ5V0DS00 (5th edition)
Date Published September 1998 NS CP(K)
Printed in Japan
The mark
•
shows major revised points.
©
1996,1997
µ
PD464318L, 464336L
Pin Name and Functions
Pin name
V
DD
V
SS
V
DD
Q
V
REF
K, /K
SA0 to SA17
DQa1 to DQb9
/SS
/SW
/SBa
/SBb
/G
ZQ
NC
TMS
TDI
TCK
TDO
Description
Core Power Supply
Ground
Output Power Supply
Input Reference
Main Clock Input
Synchronous Address Input
Synchronous Data Input / Output
Synchronous Chip Select
Synchronous Byte Write Enable
Synchronous Byte "a" Write Enable
Synchronous Byte "b" Write Enable
Asynchronous Output Enable
Output Impedance Control
No Connection
Test Mode Select (JTAG)
Test Data Input (JTAG)
Test Clock Input (JTAG)
Test Data Output (JTAG)
Write DQa1 to DQa9
Write DQb1 to DQb9
Asynchronous input
Logically selects SRAM
Supplies power for output buffers
Function
Supplies power for RAM core
3
µ
PD464318L, 464336L
Pin Name and Functions
Pin name
V
DD
V
SS
V
DD
Q
V
REF
K, /K
SA0 to SA16
DQa1 to DQd9
/SS
/SW
/SBa
/SBb
/SBc
/SBd
/G
ZQ
NC
TMS
TDI
TCK
TDO
Description
Core Power Supply
Ground
Output Power Supply
Input Reference
Main Clock
Synchronous Address Input
Synchronous Data Input / Output
Synchronous Chip Select
Synchronous Byte Write Enable
Synchronous Byte "a" Write Enable
Synchronous Byte "b" Write Enable
Synchronous Byte "c" Write Enable
Synchronous Byte "d" Write Enable
Asynchronous Output Enable
Output Impedance Control
No Connection
Test Mode Select (JTAG)
Test Data Input (JTAG)
Test Clock Input (JTAG)
Test Data Output (JTAG)
Write DQa1 to DQa9
Write DQb1 to DQb9
Write DQc1 to DQc9
Write DQd1 to DQd9
Asynchronous input
Logically selects SRAM
Supplies power for output buffers
Function
Supplies power for RAM core
5
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