TRU050TGCNA25.248 datasheet, PDF

Datasheet> All Categories > Analog mixed-signal IC> The signal circuit> TRU050TGCNA25.248

TRU050TGCNA25.248: DescriptionPhase Locked Loop, CDIP16, ROHS COMPLIANT, HERMETIC SEALED, CERAMIC, DIP-16; CategoryAnalog mixed-signal IC The signal circuit; File Size173KB，14 Pages; ManufacturerVectron International, Inc.; Websitehttp://www.vectron.com/; Environmental Compliance

Download Datasheet Parametric View All

TRU050TGCNA25.248 Overview

Phase Locked Loop, CDIP16, ROHS COMPLIANT, HERMETIC SEALED, CERAMIC, DIP-16

TRU050TGCNA25.248 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Vectron International, Inc.
Parts packaging code	DIP
package instruction	DIP,
Contacts	16
Reach Compliance Code	compliant
Analog Integrated Circuits - Other Types	PHASE LOCKED LOOP
JESD-30 code	R-CDIP-T16
JESD-609 code	e4
length	20.32 mm
Humidity sensitivity level	1
Number of functions	1
Number of terminals	16
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	4.69 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
Temperature level	COMMERCIAL
Terminal surface	GOLD OVER NICKEL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	40
width	7.62 mm

Preview

Download Datasheet

View All

TRU050

Complete VCXO based Phase-Locked Loop

Features

•

Output Frequencies to 65.536 MHz

•

5.0 V or 3.3Vdc Operation

•

Tri-State Output

•

Holdover on Loss of Signal Alarm

•

VCXO with CMOS Outputs

•

0/70° or –40/85°C Temperature Range

•

Ceramic SMD Package

•

RoHS/Lead Free Compliant

The TRU050, VCXO based PLL

Description

The VI TRU050 is a user-configurable crystal-

based PLL integrated circuit. It includes a digital

phase detector, op-amp, VCXO and additional

integrated functions for use in digital

synchronization applications. Loop filter software

is available as well SPICE models for circuit

simulation.

Applications

•

Frequency Translation

•

Clock Smoothing

•

NRZ Clock Recovery

•

DSLAM, ADM, ATM, Aggregation, Optical

Switching/Routing, Base Station

•

Low Jitter PLL’s

Figure 1. TRU050 Block Diagram

Vectron International, 267 Lowell Rd, Hudson NH 03051-4916

Page 1 of 14

Tel: 1-88-VECTRON-1

•

Web:

www.vectron.com

Rev : 06Jan2006

TRU050, VCXO Based PLL

TRU050 Theory of Operation

Phase Detector

The phase detector has two buffered inputs, DATAIN and CLKIN, which are designed to switch at 1.4

volts. DATAIN is designed to accept an NRZ data stream but may also be used for clock signals which

have about a 50% duty cycle. CLKIN is connected to OUT1 or OUT2, or a divided version of one of these

outputs. CLKIN and DATAIN and are protected by ESD diodes and should not exceed the power supply

voltage or ground by more than a few hundred millivolts.

The phase detector is basically a latched flip flop/exclusive-or gate/differential amplifier filter design to

produce a DC signal proportional to the phase between the CLKIN and DATAIN signals, see figure 4 for a

block diagram and figure 5 for a open loop transfer curve. This simplies the PLL design as the designer

does not have to filter narrow pulse signal to a DC level. Under locked conditions the rising edge CLKIN

will be centered in the middle of the DATAIN signal, see figure 6.

The phase detector gain is 0.53V/rad x data density for 5volt operation, and 0.35V/rad x data density for

3.3 volt operation. Data density = 1.0 for clock signals and is system dependent on coding and design

for NRZ signals, but 0.25 could be used as a starting point for data density.

The phase detector output is a DC signal for DATAIN frequencies greater than 1MHz but produces

signficant ripple when inputs are less than 200kHz. Additional filtering is required for low input frequency

applications such as 8kHz frequency translation, see figures 8 and 9.

Under closed loop conditions the active filter has a blocking capacitor which provides a very high DC

gain, so under normal locked conditions and input frequencies >1MHz, PHO will be about V

/2 and will

not vary signifigantly with changes in input frequency (within lock range). The control (voltage pin 1) will

vary according to the input frequency offset, but PHO will remain relatively constant.

Data In

(pin 7)

Clock In

(pin 9)

30 kΩ

20 kΩ

PHO

(pin 6)

Gain = 5 V / 2π

Gain = 2 / 3

Figure 4. Simplified Phase Detector Block Diagram

Vectron International, 267 Lowell Rd, Hudson NH 03051-4916

Page 4 of 14

Tel: 1-88-VECTRON-1

•

Web:

www.vectron.com

Rev : 06Jan2006

Recommended Resources

Exhaust gas concentration detection circuit diagram

Diamond FB-40 luxury wall fan circuit diagram

32-wire to 1-wire multiplexer circuit

The most practical basic diagram circuit 53 - partial pressure temperature protection relay circuit

Differential Franklin Oscillator

Telephone schematic diagram 05

What is the definition of the standard naming method for chip capacitors?: What is the standard naming method for chip capacitors?There are some differences between the naming methods of chip capacitors in China and abroad, but the parameters involved are the same. Parameter...; pingshang13 Test/Measurement

Arteli-AT32F4xx_Timer 7-way PWM output: Example Purpose:Use TMR1 to output 7 PWM channels simultaneously. Supported models:AT32F4xx full series 1 Quick Use Instructions1.1 Hardware ResourcesAT-START-F403A V1.0 Experimental Board 1.2 Softwar...; 火辣西米秀 Domestic Chip Exchange

Borrowing flowers to offer to Buddha: I would like to express my best wishes to you all through this forum post! May you achieve greater success in the new year! [[i] This post was last edited by lixiaohai8211 on 2010-2-13 16:30[/i]]...; lixiaohai8211 Talking

Defense and Aerospace Receiver Introduction Coming: There are also many changes happening in the defense and space RFFE space. Especially in the areas of military radar, satellite communications, electronic warfare communications, and digital receivers...; alan000345 RF/Wirelessly

Four-layer PCB board learning - modified version after guidance~~: After I finished drawing the board, I posted it here: [url]https://bbs.eeworld.com.cn/thread-462898-1-1.html[/url] riverpeak looked at it and pointed out some inappropriate places and some suggestions...; okhxyyo PCB Design

Why can't I open and create files in wince5.0 when reading and writing files written in C#2005?: I just need to read and write .TXT files. Can someone tell me how to write it? Thanks....; ljyfunkey Embedded System

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

Popular Components