No. AN7275.1
March 1997
Application Note
User’s Guide to the CDP1879 and CDP1879C1 CMOS
Real-Time Clocks
Author: D. Derkach
Introduction
The CDP1879 and CDP1879C1 Real-Time Clocks [1] are 24
pin devices, each consisting essentially of a long string of
counters that supply standard clock time and date informa-
tion in BCD format, Figure 1. In addition, the CDP1879
features an alarm circuit that activates the interrupt output
pin and a separate clock output pin that provides a program-
mable square-wave output signal. Both the internal-alarm
and clock-out signals can trigger the interrupt output pin, so
that a status register is available to indicate the interrupt
source. Users can supply a signal to the power-down pin
that allows the interrupt-output pin level to control external
power-down and wake-up circuits. Software generally
required by other real-time clocks to prevent clock rollover is
eliminated by a transparent “freeze” circuit that assures data
integrity when accessing the clock. The clock’s counters,
plus a control register that regulates operation, are
individually selectable using three address lines. Internal
control signals governing read and write operations are
selected through the IO/MEM pin, which places the device in
a memory-mapped or I/O-mapped mode of operation.
The real time clocks were designed using Intersil PaCMOS
standard-cell approach and are manufactured under a
silicon-gate CMOS process. Both the CDP1879 and
CDP1879C1 have guaranteed dc and dynamic parameters
that allow operation at temperatures of -40
o
C to +85
o
C in a
plastic package. In addition, both versions can operate in a
ceramic package from -55
o
C to 125
o
C (see data sheet [1] for
complete static and dynamic values).
The CDP1879 operates from a supply of 4V to 10.5V. It
accepts a parallel resonant crystal or will keep time with an
external
clock
source.
Crystal
frequencies
are
1.048576MHz, 2.097152MHz, and 4.194304MHz. The
CDP1879C1 is the lower voltage version with an operating
voltage range of 4V to 6.5V. Like the CDP1879, it also oper-
ates with either an external clock source or at the same crys-
tal frequencies. It can also run with a 32,768Hz crystal.
labels on the clocks, Figure 2, match the pin names of these
processors. Figure 3 indicates clock I/O control and direction
pins; the functions of these pins are explained immediately
below. Figure 4 is an I/O control and device-enabled
schematic. Table 1 shows I/O pin connections.
TPA (Timing Pulse A) -
TPA refers to a timing signal from
the CDP1800-series processors that occurs early in the
machine cycle, and that is used to latch the processor’s
multiplexed high-order address. In the real-time clock, this
pin carries a strobe input used to latch the value of the CS
pin. In memory-mapped operation, the pin may be tied high,
requiring that CS be held for the duration of each read or
write cycle. When the I/O-mapping mode is selected, this pin
must be pulsed when the CS input is high.
CS (Chip Select) -
The chip-select pin is an active high input
that is used to enable the clock.
IO/MEM (I/O or Memory-Mode Select) -
This pin is tied low
to place the clock in the memory-mapped mode, and high
when I/O operation is desired. Most processors will use the
memory-mapped mode of operation.
RD (Read) -
When the clock is in the memory-mapped
mode, RD is an active low signal that enables data from the
counters or status register to be placed on the data bus for
the processor to read. When the clock is in the I/O mode, the
read operation occurs when RD is high; a write operation
occurs when RD is low and TPB/WR is high.
TPB/WR (Timing Pulse B/Write) -
TPB refers to a timing
signal from the CDP1800-series processors that appears
late in each machine cycle and that is used to write data into
accessed peripherals. When the clock is in the memory-
mapped mode, TPB/WR is an active low signal used to write
data into the clock’s counters or control register. During I/O-
mapping, a high level on this pin allows data latched on the
trailing edge of the signal to be written into the counters or
register.
CD1800-Series Interface
The clocks interface to CDP1800-series processors that use
memory-mapping
and
I/O-mapping
techniques
to
communicate with peripherals and memory. Memory-map-
ping implies address-line decoding to select memory
locations and chip selects. With this technique, the real-time
Interfacing - Hardware Considerations
I/O-Control and Device-Enable Pins
The real-time clocks, shown in block diagram form in Figure
1, are designed to interface directly to Intersil CDP1800-
series processors (described briefly below). Therefore, pin
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7-70
Application Note 7275
clock’s counters and registers are treated as memory
locations. Read and write signals are active low. The
CDP1800-series processors include three separate N-lines
that are active during the 14 I/O instructions. These
instructions are memory referenced so that data traveling in
either direction is transferred between the peripherals and
memory.
When I/O instructions are executed, the memory location is
the reference for data transfer. Therefore, when an output
instruction is performed (write cycle) the processor’s RD line
is activated and puts the data in memory onto the data bus.
Late in the same cycle, the TPB from the processor is used
to write data into the peripheral. An input instruction (read
cycle) allows external data to be placed in memory. The pro-
cessor’s WR line is activated, and the data is written in.
AM - PM AND
HOUR
LOGIC
FREEZE
CIRCUIT
CALENDAR
LOGIC
XTAL
XTAL
OSCILLATOR
PRESCALE
SECOND
MINUTE
HOUR
DAY
MONTH
PRESCALE
SELECT
CLOCK
SELECT
CLOCK OUT
INT
RESET
V
DD
V
SS
CLOCK
AND
INT
LOGIC
CONTROL
REGISTER
8-BIT DATA BUS
COMPARATOR
SECOND
LATCH
MINUTE
LATCH
HOUR
LATCH
INT. STATUS
REGISTER
DB0-DB7
I/O
INTER-
FACE
A0
A1
A2
TPA
IO/MEM
TPB/WR
RD
CS
POWER DOWN
ADDRESS DECODE
AND
CONTROL LOGIC
FIGURE 1. BLOCK DIAGRAM OF REAL-TIME CLOCK
XTAL CONNECTIONS
DATA DIRECTIONAL SIGNALS
SELECTS DEVICE
SELECTS OPERATIONAL MODE
POWER DOWN SELECT
INITIALIZES DEVICE
XTAL
CLK
OUT
XTAL
A0
TPB/WR
A1
RD
A2
TPA
CS
IO/MEM
PWR
DOWN
RESET
INT
SQUARE-WAVE OUTPUT
ADDRESS INPUTS
CHIP-SELECT
GATE AND LATCH
INTERRUPT OUTPUT
DB0
TO
DB7
BIDIRECTIONAL
DATA BUS
FIGURE 2. REAL-TIME-CLOCK PIN FUNCTIONS
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FPGA/CPLD
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