HIGH SPEED
1K X 8 DUAL-PORT
STATIC SRAM
Features
High-speed access
– Commercial: 20/25/35/55/100ns (max.)
– Industrial: 25/55/100ns (max.)
– Military: 25/35/55/100ns (max.)
Low-power operation
– IDT7130/IDT7140SA
—
Active: 550mW (typ.)
—
Standby: 5mW (typ.)
– IDT7130/IDT7140LA
—
Active: 550mW (typ.)
—
Standby: 1mW (typ.)
MASTER IDT7130 easily expands data bus width to 16-or-
more-bits using SLAVE IDT7140
IDT7130SA/LA
IDT7140SA/LA
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
On-chip port arbitration logic (IDT7130 Only)
BUSY
output flag on IDT7130;
BUSY
input on IDT7140
INT
flag for port-to-port communication
Fully asynchronous operation from either port
Battery backup operation–2V data retention (LA only)
TTL-compatible, single 5V ±10% power supply
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Available in 48-pin DIP, LCC and Ceramic Flatpack, 52-pin
PLCC, and 64-pin STQFP and TQFP
Green parts available, see ordering information
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
7L
I/O
Control
BUSY
L
(1,2)
I/O
0R
-I/O
7R
I/O
Control
BUSY
R
Address
Decoder
10
,
(1,2)
A
9L
A
0L
MEMORY
ARRAY
10
Address
Decoder
A
9R
A
0R
CE
L
OE
L
R/W
L
ARBITRATION
and
INTERRUPT
LOGIC
CE
R
OE
R
R/W
R
INT
L
(2)
INT
R
2689 drw 01
(2)
NOTES:
1. IDT7130 (MASTER):
BUSY
is open drain output and requires pullup resistor.
IDT7140 (SLAVE):
BUSY
is input.
2. Open drain output: requires pullup resistor.
APRIL 2006
1
DSC-2689/13
©2006 Integrated Device Technology, Inc.
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Description
The IDT7130/IDT7140 are high-speed 1K x 8 Dual-Port Static
RAMs. The IDT7130 is designed to be used as a stand-alone 8-bit
Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the
IDT7140 "SLAVE" Dual-Port in 16-bit-or-more word width systems.
Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-or-
more-bit memory system applications results in full-speed, error-
free operation without the need for additional discrete logic.
Both devices provide two independent ports with separate con-
trol, address, and I/O pins that permit independent asynchronous
access for reads or writes to any location in memory. An automatic
power down feature, controlled by
CE,
permits the on chip circuitry
of each port to enter a very low standby power mode.
Fabricated using IDT's CMOS high-performance tech-nology,
these devices typically operate on only 550mW of power. Low-
power (LA) versions offer battery backup data retention capability,
with each Dual-Port typically consuming 200µW from a 2V battery.
The IDT7130/IDT7140 devices are packaged in 48-pin sidebraze
or plastic DIPs, LCCs, flatpacks, 52-pin PLCC, and 64-pin TQFP
and STQFP. Military grade products are manufactured in compli-
ance with the latest revision of MIL-PRF-38535 QML, making it
ideally suited to military temperature applications demanding the
highest level of performance and reliability.
Pin Configurations
(1,2,3)
01/08/02
CE
L
R/W
L
BUSY
L
INT
L
OE
L
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
I/O
4L
I/O
5L
I/O
6L
I/O
7L
GND
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
IDT7130/40
41
P or C
9
40
P48-1
(4)
10
39
&
11
C48-2
(4)
38
12
48-Pin
37
DIP
13
36
Top View
(5)
35
14
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
V
CC
CE
R
R/W
R
BUSY
R
INT
R
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
I/O
7R
I/O
6R
I/O
5R
I/O
4R
I/O
3R
I/O
2R
I/O
1R
I/O
0R
2689 drw 02
01/
IN
,
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. P48-1 package body is approximately .55 in x .61 in x .19 in.
C48-2 package body is approximately .62 in x 2.43 in x .15 in.
L48-1 package body is approximately .57 in x .57 in x .68 in.
F48-1 package body is approximately .75 in x .75 in x .11 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
2
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
01/08/02
INDEX
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
I/O
3L
8
9
10
11
12
13
14
15
16
17
18
19
20
A
0L
OE
L
N/C
INT
L
BUSY
L
R/W
L
CE
L
V
CC
7 6 5 4 3 2
1
52 51 50 49 48 47
46
45
44
43
42
41
40
39
38
37
36
35
34
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
N/C
I/O
7R
,
2689 drw 04
IDT7130/40J
J52-1
(4)
52-Pin PLCC
Top View
(5)
21 22 23 24 25 26 27 28 29 30 31 32 33
01/08/02
INDEX
OE
L
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
N/C
A
7L
A
8L
A
9L
N/C
I/O
0L
I/O
1L
I/O
2L
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
N/C
N/C
N/C
INT
L
BUSY
L
R/W
L
CE
L
V
CC
V
CC
CE
R
R/W
R
BUSY
R
INT
R
N/C
N/C
N/C
I/O
4L
I/O
5L
I/O
6L
I/O
7L
N/C
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
CE
R
R/W
R
BUSY
R
INT
R
N/C
Pin Configurations
(1,2,3)
(con't.)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
IDT7130/40TF or PF
PP64-1 & PN64-1
(4)
64-Pin STQFP
64-Pin TQFP
Top View
(5)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
N/C
A
7R
A
8R
A
9R
N/C
N/C
I/O
7R
I/O
6R
,
2689 drw 05
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J52-1 package body is approximately .75 in x .75 in x .17 in.
PP64-1 package body is approximately 10 mm x 10 mm x 1.4mm.
PN64-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
I/O
3L
N/C
I/O
4L
I/O
5L
I/O
6L
I/O
7L
N/C
GND
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
N/C
I/O
4R
I/O
5R
3
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect
to GND
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
& Industrial
-0.5 to +7.0
Military
-0.5 to +7.0
Unit
V
Recommended DC Operating
Conditions
Symbol
V
CC
GND
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5
(1)
Typ.
5.0
0
____
____
Max.
5.5
0
6.0
(2)
0.8
Unit
V
V
V
V
2689 tbl 02
T
BIAS
T
STG
I
OUT
-55 to +125
-65 to +150
50
-65 to +135
-65 to +150
50
o
C
C
V
IH
V
IL
o
mA
2689 tbl 01
NOTES:
1. V
IL
(min.) > -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 10%.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of the specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> Vcc + 10%.
Recommended Operating
Temperature and Supply Voltage
(1)
Grade
Military
Commercial
Ambient
Temperature
-55
O
C to +125
O
C
0
O
C to +70
O
C
-40
O
C to +85
O
C
GND
0V
0V
0V
Vcc
5.0V
+
10%
5.0V
+
10%
5.0V
+
10%
2689 tbl 03
Capacitance
Symbol
C
IN
C
OUT
(T
A
= +25°C, f = 1.0MHz)
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
2689 tbl 05
Industrial
STQFP and TQFP Packages Only
Parameter
(1)
Input Capacitance
Output Capacitance
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
CC
= 5.0V ± 10%)
7130SA
7140SA
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
(1)
Output Low Voltage (I/O
0
-I/O
7
)
Open Drain Output
Low Voltage (BUSY,
INT)
Output High Voltage
Test Conditions
V
CC
= 5.5V, V
IN
= 0V to V
CC
V
CC
- 5.5V,
CE
= V
IH
, V
OUT
= 0V to V
CC
I
OL
= 4mA
I
OL
= 16mA
I
OH
= -4mA
Min.
___
7130LA
7140LA
Min.
___
Max.
10
10
0.4
0.5
___
Max.
5
5
0.4
0.5
___
Unit
µA
µA
V
V
V
2689 tbl 04
___
___
___
___
___
___
2.4
2.4
NOTE:
1. At Vcc
<
2.0V leakages are undefined.
4
IDT7130SA/LA and IDT7140SA/LA
High-Speed 1K x 8 Dual-Port Static SRAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1,5)
(V
CC
= 5.0V ± 10%)
7130X20
(2)
7140X20
(2)
Com'l Only
Symbol
I
CC
Parameter
Dynamic Operating
Current
(Both Ports Active)
Test Condition
CE
L
and
CE
R
= V
IL
,
Outputs Disabled
f = f
MAX
(3)
Version
COM'L
MIL &
IND
COM'L
MIL &
IND
I
SB2
Standby Current
(One Port - TTL
Level Inputs)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(6)
Active Port OutputsDisabled,
f=f
MAX
(3)
COM'L
MIL &
IND
COM'L
MIL &
IND
COM'L
MIL &
IND
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
Typ.
110
110
____
____
7130X25
7140X25
Com'l, Ind
& Military
Typ.
110
110
110
110
30
30
30
30
65
65
65
65
1.0
0.2
1.0
0.2
60
60
60
60
Max.
220
170
280
220
65
45
80
60
150
115
160
125
15
5
30
10
145
105
155
115
7130X35
7140X35
Com'l
& Military
Typ.
110
110
110
110
25
25
25
25
50
50
50
50
1.0
0.2
____
____
Max.
250
200
____
____
Max.
165
120
230
170
65
45
80
60
125
90
150
115
30
10
____
____
Unit
mA
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
CE
L
and
CE
R
= V
IH
f = f
MAX
(3)
30
30
____
____
65
45
____
____
mA
65
65
____
____
165
125
____
____
mA
I
SB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
CE
L
and
CE
R
> V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(4)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(6)
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled,
f = f
MAX
(3)
1.0
0.2
____
____
15
5
____
____
mA
I
SB4
Full Standby Current
(One Port -
CMOS Level Inputs)
60
60
____
____
155
115
____
____
45
45
45
45
110
85
145
105
mA
2689 tbl 06a
7130X55
7140X55
Com'l, Ind
& Military
Symbol
I
CC
Parameter
Dynamic Operating
Current
(Both Ports Active)
CE
L
and
CE
R
= V
IL
,
Outputs Disabled
f = f
MAX
(3)
Test Condition
Version
COM'L
MIL &
IND
COM'L
MIL &
IND
I
SB2
Standby Current
(One Port - TTL
Level Inputs)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(6)
Active Port Outputs Disabled,
f=f
MAX
(3)
COM'L
MIL &
IND
COM'L
MIL &
IND
COM'L
MIL &
IND
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
SA
LA
Typ.
110
110
110
110
20
20
20
20
40
40
40
40
1.0
0.2
1.0
0.2
40
40
40
40
Max.
155
110
190
140
65
35
65
45
110
75
125
90
15
4
30
10
100
70
110
85
7130X100
7140X100
Com'l, Ind
& Military
Typ.
110
110
110
110
20
20
20
20
40
40
40
40
1.0
0.2
1.0
0.2
40
40
40
40
Max.
155
110
190
140
55
35
65
45
110
75
125
90
15
4
30
10
95
70
110
80
mA
mA
mA
mA
Unit
mA
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
CE
L
and
CE
R
= V
IH
f = f
MAX
(3)
I
SB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
CE
L
and
CE
R
> V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(4)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(6)
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled,
f = f
MAX
(3)
I
SB4
Full Standby Current
(One Port -
CMOS Level Inputs)
2689 tbl 06b
NOTES:
1. 'X' in part numbers indicates power rating (SA or LA).
2. PLCC , TQFP and STQFP packages only.
3. At f = f
MAX
, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t
CYC
, and using “AC TEST CONDITIONS” of input levels
of GND to 3V.
4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
5. Vcc = 5V, T
A
=+25°C for Typ and is not production tested. Vcc DC = 100 mA (Typ)
6. Port "A" may be either left or right port. Port "B" is opposite from port "A".
5
Microchip MCU
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