LF
PA
K
PSMN3R0-30MLC
N-channel 30 V 3.15 mΩ logic level MOSFET in LFPAK33
using NextPower Technology
Rev. 4 — 15 June 2012
Product data sheet
1. Product profile
1.1 General description
Logic level enhancement mode N-channel MOSFET in LFPAK33 package. This product is
designed and qualified for use in a wide range of industrial, communications and domestic
equipment
33
1.2 Features and benefits
Low parasitic inductance and
resistance
Optimised for 4.5V Gate drive utilising
NextPower Superjunction technology
Ultra low QG, QGD, & QOSS for high
system efficiencies at low and high
loads
1.3 Applications
DC-to-DC converters
Load switching
Synchronous buck regulator
1.4 Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
T
j
R
DSon
Quick reference data
Parameter
drain-source voltage
drain current
total power dissipation
junction temperature
drain-source on-state
resistance
V
GS
= 4.5 V; I
D
= 25 A; T
j
= 25 °C;
see
Figure 10
V
GS
= 10 V; I
D
= 25 A; T
j
= 25 °C;
see
Figure 10
Dynamic characteristics
Q
GD
Q
G(tot)
gate-drain charge
total gate charge
V
GS
= 4.5 V; I
D
= 25 A; V
DS
= 15 V;
see
Figure 12;
see
Figure 13
V
GS
= 4.5 V; I
D
= 25 A; V
DS
= 15 V;
see
Figure 12;
see
Figure 13
-
-
4.3
16.1
-
-
nC
nC
Conditions
T
j
= 25 °C
T
mb
= 25 °C; V
GS
= 10 V; see
Figure 1
T
mb
= 25 °C; see
Figure 2
[1]
Min
-
-
-
-55
-
-
Typ
-
-
-
-
3.5
2.7
Max
30
70
88
175
4.05
3.15
Unit
V
A
W
°C
mΩ
mΩ
Static characteristics
[1]
Continuous current is limited by package.
NXP Semiconductors
PSMN3R0-30MLC
N-channel 30 V 3.15mΩ logic level MOSFET in LFPAK33 using NextPower Technology
2. Pinning information
Table 2.
Pin
1
2
3
4
mb
Pinning information
Symbol Description
S
S
S
G
D
source
source
source
gate
mounting base; connected to
drain
1
2
3
4
mbb076
Simplified outline
Graphic symbol
D
G
S
SOT1210 (LFPAK33)
3. Ordering information
Table 3.
Ordering information
Package
Name
PSMN3R0-30MLC
LFPAK33
Description
Plastic single ended surface mounted package (LFPAK33);
4 leads
Version
SOT1210
Type number
4. Limiting values
Table 4.
Symbol
V
DS
V
GS
I
D
I
DM
P
tot
T
stg
T
j
T
sld(M)
V
ESD
I
S
I
SM
E
DS(AL)S
Limiting values
Parameter
drain-source voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
peak soldering temperature
electrostatic discharge voltage
source current
peak source current
non-repetitive drain-source
avalanche energy
MM (JEDEC JESD22-A115)
T
mb
= 25 °C
pulsed; t
p
≤
10 µs; T
mb
= 25 °C
V
GS
= 10 V; T
j(init)
= 25 °C; I
D
= 70 A;
V
sup
≤
30 V; R
GS
= 50
Ω;
unclamped;
see
Figure 3
[1]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Conditions
T
j
= 25 °C
V
GS
= 10 V; T
mb
= 25 °C; see
Figure 1
V
GS
= 10 V; T
mb
= 100 °C; see
Figure 1
pulsed; t
p
≤
10 µs; T
mb
= 25 °C;
see
Figure 4
T
mb
= 25 °C; see
Figure 2
[1]
[1]
Min
-
-20
-
-
-
-
-55
-55
-
350
-
-
-
Max
30
20
70
70
498
88
175
175
260
-
70
498
64
Unit
V
V
A
A
A
W
°C
°C
°C
V
A
A
mJ
Source-drain diode
Avalanche ruggedness
[1]
Continuous current is limited by package.
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
PSMN3R0-30MLC
Product data sheet
Rev. 4 — 15 June 2012
2 of 14
NXP Semiconductors
PSMN3R0-30MLC
N-channel 30 V 3.15mΩ logic level MOSFET in LFPAK33 using NextPower Technology
160
I
D
(A)
120
003aaj595
120
P
der
(%)
80
03na19
80
(1)
40
40
0
0
50
100
150
T
mb
200
(°C)
0
0
50
100
150
T
mb
(°C)
200
Fig 1.
Continuous drain current as a function of
mounting base temperature
10
2
I
AL
(A)
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
003aaj596
(1)
10
(2)
1
10
-3
10
-2
10
-1
1
t
AL
(ms)
10
Fig 3.
Single pulse avalanche rating; avalanche current as a function of avalanche time
PSMN3R0-30MLC
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 15 June 2012
3 of 14
NXP Semiconductors
PSMN3R0-30MLC
N-channel 30 V 3.15mΩ logic level MOSFET in LFPAK33 using NextPower Technology
10
3
I
D
(A)
Limit R
DSon
= V
DS
/ I
D
10
2
t
p
=10
μ
s
100
μ
s
003aaj597
10
DC
1 ms
1
10 ms
100 ms
10
-1
10
-1
1
10
V
DS
(V)
10
2
Fig 4.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
Thermal characteristics
Parameter
see
Figure 5
Conditions
Min
-
Typ
1.49
Max
1.7
Unit
K/W
thermal resistance from junction to mounting base
10
Z
th(j-mb)
(K/W)
1
δ
= 0.5
0.2
0.1
10
-1
0.05
0.02
10
-2
P
003aaj598
δ=
t
p
T
single shot
t
p
T
t
10
-3
10
-6
10
-5
10
-4
10
-3
10
-2
10
-1
t
p
(s)
1
Fig 5.
Transient thermal impedance from junction to mounting base as a function of pulse duration
PSMN3R0-30MLC
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 15 June 2012
4 of 14
NXP Semiconductors
PSMN3R0-30MLC
N-channel 30 V 3.15mΩ logic level MOSFET in LFPAK33 using NextPower Technology
6. Characteristics
Table 6.
Symbol
V
(BR)DSS
V
GS(th)
∆V
GS(th)
/∆T
Characteristics
Parameter
drain-source
breakdown voltage
gate-source threshold
voltage
gate-source threshold
voltage variation with
temperature
drain leakage current
gate leakage current
drain-source on-state
resistance
V
DS
= 30 V; V
GS
= 0 V; T
j
= 25 °C
V
DS
= 30 V; V
GS
= 0 V; T
j
= 150 °C
I
GSS
R
DSon
V
GS
= 16 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -16 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= 4.5 V; I
D
= 25 A; T
j
= 25 °C;
see
Figure 10
V
GS
= 4.5 V; I
D
= 25 A; T
j
= 150 °C;
see
Figure 10;
see
Figure 11
V
GS
= 10 V; I
D
= 25 A; T
j
= 25 °C;
see
Figure 10
V
GS
= 10 V; I
D
= 25 A; T
j
= 150 °C;
see
Figure 10;
see
Figure 11
R
G
Q
G(tot)
gate resistance
total gate charge
f = 1 MHz
I
D
= 25 A; V
DS
= 15 V; V
GS
= 10 V;
see
Figure 12;
see
Figure 13
I
D
= 25 A; V
DS
= 15 V; V
GS
= 4.5 V;
see
Figure 12;
see
Figure 13
I
D
= 0 A; V
DS
= 0 V; V
GS
= 10 V
Q
GS
Q
GS(th)
Q
GS(th-pl)
Q
GD
V
GS(pl)
C
iss
C
oss
C
rss
gate-source charge
pre-threshold
gate-source charge
post-threshold
gate-source charge
gate-drain charge
gate-source plateau
voltage
input capacitance
output capacitance
reverse transfer
capacitance
I
D
= 25 A; V
DS
= 15 V;
see
Figure 12;
see
Figure 13
V
DS
= 15 V; V
GS
= 0 V; f = 1 MHz;
T
j
= 25 °C; see
Figure 14
I
D
= 25 A; V
DS
= 15 V; V
GS
= 4.5 V;
see
Figure 12;
see
Figure 13
Dynamic characteristics
-
-
-
-
-
-
-
-
-
-
-
34.8
16.1
32.3
6.2
3.7
2.5
4.3
2.9
2330
480
180
-
-
-
-
-
-
-
-
-
-
-
nC
nC
nC
nC
nC
nC
nC
V
pF
pF
pF
Conditions
I
D
= 250 µA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 250 µA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25 °C
Min
30
27
1.45
-
Typ
-
-
1.74
-4
Max
-
-
2.15
-
Unit
V
V
V
mV/K
Static characteristics
I
DSS
-
-
-
-
-
-
-
-
0.37
-
-
-
-
3.5
-
2.7
-
0.74
1
100
100
100
4.05
6.9
3.15
5.35
1.48
µA
µA
nA
nA
mΩ
mΩ
mΩ
mΩ
Ω
PSMN3R0-30MLC
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 4 — 15 June 2012
5 of 14
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