TSPC603EVAU5LN datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> TSPC603EVAU5LN

TSPC603EVAU5LN: DescriptionRISC Microprocessor, 32-Bit, 133MHz, CMOS, CQFP240, CERAMIC, LCC-240; CategoryThe embedded processor and controller Microcontrollers and processors; File Size632KB，38 Pages; Manufacturere2v technologies

Download Datasheet Parametric View All

TSPC603EVAU5LN Overview

RISC Microprocessor, 32-Bit, 133MHz, CMOS, CQFP240, CERAMIC, LCC-240

TSPC603EVAU5LN Parametric

Parameter Name	Attribute value
Maker	e2v technologies
Parts packaging code	QFP
package instruction	,
Contacts	240
Reach Compliance Code	unknown
ECCN code	3A001.A.3
Address bus width	32
bit size	32
boundary scan	YES
maximum clock frequency	66.67 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-CQFP-G240
low power mode	YES
Number of terminals	240
Package body material	CERAMIC, METAL-SEALED COFIRED
Package shape	SQUARE
Package form	FLATPACK
Certification status	Not Qualified
speed	133 MHz
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Terminal form	GULL WING
Terminal location	QUAD
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

Preview

Download Datasheet

View All

TSPC603E

PowerPC 603e™ RISC MICROPROCESSOR Family

PID6-603e Specification

DESCRIPTION

The PID6-603e implementation of PC603e (after named 603e)

is a low-power implementation of reduced instruction set com-

puter (RISC) microprocessors PowerPC™ family. The 603e

implements 32-bit effective addresses, integer data types of 8,

16 and 32 bits, and floating-point data types of 32 and 64 bits.

The 603e is a low-power 3.3-volt design and provides four soft-

ware controllable power-saving modes.

The 603e is a superscalar processor capable of issuing and

retiring as many as three instructions per clock. Instructions

can execute out of order for increased performance ; however,

the 603e makes completion appear sequential. The 603e inte-

grates five execution units and is able to execute five instruc-

tions in parallel.

The 603e provides independent on-chip, 16-Kbyte, four-way

set-associative, physically addressed caches for instructions

and data and on-chip instruction and data memory manage-

ment units (MMUs). The MMUs contain 64-entry, two-way set-

associative, data and instruction translation lookaside buffers

that provide support for demand-paged virtual memory

address translation and variable-sized block translation.

The 603e has a selectable 32 or 64-bit data bus and a 32-bit

address bus. The 603e interface protocol allows multiple mas-

ters to complete for system resources through a central exter-

nal arbiter. The 603e supports single-beat and burst data

transfers for memory accesses, and supports memory-

mapped I/O.

The 603e uses an advanced, 3.3-V CMOS process technology

and maintains full interface compatibility with TTL devices.

The 603e integrates in system testability and debugging fea-

tures through JTAG boundary-scan capability.

CERQUAD 240

A suffix

CERQUAD 240

Ceramic Leaded Chip Carrier

MAIN FEATURES

2.4 SPECint95, 2.1 SPECfp95 @ 100 MHz (estimated)

Superscalar (3 instructions per clock peak).

Dual 16KB caches.

Selectable bus clock.

32-bit compatibility PowerPC implementation.

On chip debug support.

typical = 3.2 Watts (100 MHz), full operating conditions.

Nap, doze and sleep modes for power savings.

Branch folding.

64-bit data bus (32-bit data bus option).

4-Gbyte direct addressing range.

Pipelined single/double precision float unit.

IEEE 754 compatible FPU.

IEEE P 1149-1 test mode (JTAG/C0P).

int

max = 100/120/133 MHz.

bus

max = 66 MHz.

Compatible CMOS input

TTL Output.

G suffix

CBGA 255

Ceramic Ball Grid Array

SCREENING / QUALITY / PACKAGING

This product is manufactured in full compliance with :

MIL-STD-883 class B or According to TCS standards

Upscreenings based upon TCS standards

Full military temperature range (T

= -55°C, T

= +125°C)

Industrial temperature range (T

–

40°C, T

= +110°C)

= 3.3 V

5 %.

240 pin Cerquad or 255 pin CBGA packages

December1998

1/38

TSPC603E

A. GENERAL DESCRIPTION

Fetch

Unit

Completion

Unit

Dispatch

Unit

Branch

Unit

Integer

Unit

Gen

Reg

Unit

Gen

Re-

name

Load/

Store

Unit

Re-

name

Reg

File

Float

Unit

D MMU

16K Data Cache

I MMU

16K Inst. Cache

Bus Interface Unit

32b

address

System Bus

64b

data

Figure 1 : Block diagram

1. INTRODUCTION

The 603e is a low-power implementation of the PowerPC microprocessor family of reduced instruction set commuter (RISC) micro-

processors. The 603e implements the 32-bit portion of the PowerPC architecture, which provides 32-bit effective addresses, integer

data types of 8, 16 and 32 bits, and floating-point data types of 32 and 64 bits. For 64-bit PowerPC microprocessors, the PowerPC

architecture provides 64-bit integer data types, 64-bit addressing, and other features required to complete the 64-bit architecture.

The 603e provides four software controllable power-saving modes. Three of the modes (the nap, doze, and sleep modes) are static in

nature, and progressively reduce the amount of power dissipated by the processor. The fourth is a dynamic power management

mode that causes the functional units in the 603e to automatically enter a low-power mode when the functional units are idle without

affecting operational performance, software execution, or any external hardware.

The 603e is a superscalar processor capable of issuing and retiring as many as three instructions per clock. Instructions can execute

out of order for increased performance ; however, the 603e makes completion appear sequential.

The 603 e integrates five execution units - an integer unit (IU), a floating-point unit (FPU), a branch processing unit (BPU), a load/store

unit (LSU) and a system register unit (SRU). The ability to execute five instructions in parallel and the use of simple instructions with

rapid execution times yield high efficiency and throughput for 603e-based systems. Most integer instructions execute in one clock

cycle. The FPU is pipelined so a single-precision multiply-add instruction can be issued every clock cycle.

The 603e provides independent on-chip, 16 Kbyte, four-way set-associative, physically addressed caches for instructions and data

and on-chip instruction and data memory management units (MMUs). The MMUs contain 64-entry, two-way set-associative, data

and instruction translation lookaside buffers (DTLB and ITLB) that provide support for demand-paged virtual memory address

translation and variable-sized block translation. The TLBs and caches use a least recently used (LRU) replacement algorithm. The

603e also supports block address translation through the use of two independent instruction and data block address translation (IBAT

and DBAT) arrays of four entries each. Effective addresses are compared simultaneously with all four entries in the BAT array during

block translation. In accordance with the PowerPC architecture, if an effective address hits in both the TLB and BAT array, the BAT

translation takes priority.

The 603e has a selectable 32 - or 64-bit - data bus and a 32-bit address bus. The 603e interface protocol allows multiple masters to

compete for system resources through a central external arbiter. The 603e provides a three-state coherency protocol that supports

the exclusive, modified, and invalid cache states. This protocol as a compatible subset of the MESI (modified/exclusive/shared/in-

valid) four-state protocol and operates coherently in systems that contain four-state caches. The 603e supports single-beat and burst

data transfers for memory accesses, and supports memory-mapped I/O.

The 603e uses an advanced, 3.3 V CMOS process technology and maintains full interface compatibility with TTL devices.

3/38

Recommended Resources

A circuit diagram integrating a charging management module

Circuit to prevent motor from running without load

SH-804 Holiday Lights ASIC

Zero detector circuit diagram

Electromechanical control compound interlocking protection motor reversible starting controller circuit

555 touch audio circuit

How does PXA270 communicate with the baseband?: How does PXA270 communicate with the baseband? Is it through the UART port to send AT Command? For example, does the phone call function send an ATD command to the baseband?...; strawberry921 Embedded System

How to set LogCat filter display on Android: I am learning Android. I would like to ask how to set LogCat to filter and display the necessary information. Because LogCat displays a lot of useless information, it is inconvenient to read. Is there...; chenbingjy Linux and Android

Five pictures from ST show the low power consumption of STM8L: Solar power supply A potato can be used for power supply. Compared with some products that use apples for display, potatoes should be more energy-efficient, haha Using RF wireless energy transmission ...; 老夫子 Energy Infrastructure?

Homemade simple LED strobe light: In the cookie-cutter DIY and MOD occasions, many players have painstakingly transformed the lighting effects to be static. If there are thousands of identical transformation MODs on Lanparty, how can ...; yuandayuan6999 DIY/Open Source Hardware

k9f2808-NandFlash debugging process and experience: Hardware platform: ARM7 44b0x Software debugging platform: ADS1.2 Purpose: Debug a NandFlash of model: Samsung's k9f2808 with a capacity of 16M * 8Bit In the text: NF means NandFlash...; zzzzer16 Embedded System

Power supply circuit diagram of SUPERSYNC PWB-1537 and SUPERSYNC EM-1428 color display: Power supply circuit diagram of SUPERSYNC PWB-1537 and SUPERSYNC EM-1428 color display...; 破茧佼龙 Power technology

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components