AS7C33512NTF36A-10BI datasheet, PDF

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AS7C33512NTF36A-10BI: DescriptionZBT SRAM, 512KX36, 10ns, CMOS, PBGA165, BGA-165; Categorystorage storage; File Size441KB，22 Pages; ManufacturerALSC [Alliance Semiconductor Corporation]

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AS7C33512NTF36A-10BI Overview

ZBT SRAM, 512KX36, 10ns, CMOS, PBGA165, BGA-165

AS7C33512NTF36A-10BI Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	ALSC [Alliance Semiconductor Corporation]
Objectid	2010856051
Parts packaging code	BGA
package instruction	TBGA, BGA165,11X15,40
Contacts	165
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
compound_id	6403340
Maximum access time	10 ns
Other features	FLOW-THROUGH ARCHITECTURE
Maximum clock frequency (fCLK)	83 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B165
JESD-609 code	e0
length	15 mm
memory density	18874368 bit
Memory IC Type	ZBT SRAM
memory width	36
Number of functions	1
Number of terminals	165
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	512KX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE
Parallel/Serial	PARALLEL
power supply	2.5/3.3,3.3 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
Maximum standby current	0.04 A
Minimum standby current	3.14 V
Maximum slew rate	0.23 mA
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	13 mm

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May 2004

AS7C33512NTF32A

AS7C33512NTF36A

3.3V 512K × 32/36 Flowthrough Synchronous SRAM with NTD

Features

•

Organization: 524,288 words × 32 or 36 bits

NTD

™1

architecture for efficient bus operation

Fast clock to data access: 8.5/10 ns

Fast OE access time: 3.4/3.8 ns

Fully synchronous operation

Flow-through mode

Asynchronous output enable control

•

Available in 100-pin TQFP and 165-ball BGA package

Byte write enables

Clock enable for operation hold

Multiple chip enables for easy expansion

3.3V core power supply

2.5V or 3.3V I/O operation with separate V

DDQ

Self-timed write cycles

Interleaved or linear burst modes

Snooze mode for standby operation

1. NTD

is a trademark of Alliance Semiconductor Corporation. All trade-

marks mentioned in this document are the property of their respective owners.

Logic block diagram

A[18:0]

Address

Burst logic

CLK

CE0

CE1

CE2

R/W

BWa

BWb

BWc

BWd

ADV / LD

LBO

32/36

Write delay

addr. registers

CLK

Control

logic

CLK

Write Buffer

CLK

512K x 32/36

SRAM

Array

DQ[a,b,c,d]

Data

Input

CLK

32/36

CLK

CEN

Output

Buffer

32/36

DQ[a,b,c,d]

Selection guide

-85

Minimum cycle time

Maximum clock access time

Maximum operating current

Maximum standby current

Maximum CMOS standby current (DC)

8.5

250

-10

230

Units

5/13/04, v 1.0

Alliance Semiconductor

P. 1 of 22

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