−10 dBm/0 dBm min/max; for lower frequencies, ensure slew
rate (SR) > 400 V/μs
For f
REFIN
< 10 MHz, ensure slew rate > 50 V/μs
For 10 MHz < f
REFIN
< 250 MHz, biased at AV
DD
/2
2
For 250 MHz < f
REFIN
< 300 MHz, biased at AV
DD
/2
2
10/300
0.4/AV
DD
0.7/AV
DD
10
±100
32
MHz min/max
V p-p min/max
V p-p min/max
pF max
μA max
MHz max
5
312.5
2.5
2.7/10
1
2
2
2
1.4
0.6
±1
10
1.4
VDD – 0.4
0.4
2.7/3.3
AV
DD
AV
DD
/5.5
29
10
−207
−137
−133
−87
mA typ
μA typ
% typ
kΩ min/max
nA typ
% typ
% typ
% typ
V min
V max
μA max
pF max
V min
V min
V max
V min/max
V min/V max
mA max
μA typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
Programmable
With R
SET
= 5.1 kΩ
With R
SET
= 5.1 kΩ
Sink and source current
0.5 V < V
CP
< V
P
– 0.5
0.5 V < V
CP
< V
P
– 0.5
V
CP
= V
P
/2
Open-drain 1 kΩ pull-up to 1.8 V
CMOS output chosen
I
OL
= 500 μA
23 mA typical
@ 10 MHz PFD frequency
@ 25 MHz PFD frequency
@ VCO output
@ 2 kHz offset, 25 MHz PFD frequency
Operating temperature of B version is −40°C to +85°C.
AC-coupling ensures AV
DD
/2 bias.
3
Guaranteed by design. Sample tested to ensure compliance.
4
This figure can be used to calculate phase noise for any application. Use the formula –207 + 10log(f
PFD
) + 20logN to calculate in-band phase noise performance as seen
at the VCO output.
5
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value).
6
The phase noise is measured with the EVAL-ADF4157EB1Z and the Agilent E5052A phase noise system.
7
f
REFIN
= 100 MHz; f
PFD
= 25 MHz; offset frequency = 2 kHz; RF
OUT
= 5800.25 MHz; N = 232; loop bandwidth = 20 kHz.
Rev. A | Page 3 of 24
ADF4157
TIMING SPECIFICATIONS
AV
DD
= DV
DD
= 2.7 V to 3.3 V; V
P
= AV
DD
to 5.5 V; AGND = DGND = 0 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted;
dBm referred to 50 Ω.
Table 2.
Parameter
t
1
t
2
t
3
t
4
t
5
t
6
t
7
Limit at T
MIN
to T
MAX
(B Version)
20
10
10
25
25
10
20
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
LE setup time
Data to clock setup time
Data to clock hold time
Clock high duration
Clock low duration
Clock to LE setup time
LE pulse width
t
4
CLK
t
5
t
2
DATA
DB23 (MSB)
DB22
t
3
DB2
(CONTROL BIT C3)
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
7
LE
t
1
LE
t
6
05874-002
Figure 2. Timing Diagram
Rev. A | Page 4 of 24
ADF4157
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, GND = AGND = DGND = 0 V, V
DD
= AV
DD
= DV
DD
, unless otherwise noted.
Table 3.
Parameter
AV
DD
/DV
DD
to AGND/DGND
AV
DD
to DV
DD
V
P
to AGND/DGND
V
P
to AV
DD
/DV
DD
Digital I/O Voltage to AGND/DGND
Analog I/O Voltage to AGND/DGND
REF
IN
, RF
IN
x to AGND/DGND
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Maximum Junction Temperature
Reflow Soldering
Peak Temperature
Time at Peak Temperature
Rating
−0.3 V to +4 V
−0.3 V to +0.3 V
−0.3 V to +5.8 V
−0.3 V to +5.8 V
−0.3 V to V
DD
+ 0.3 V
−0.3 V to V
DD
+ 0.3 V
−0.3 V to V
DD
+ 0.3 V
−40°C to +85°C
−65°C to +125°C
150°C
260°C
40 sec
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
TSSOP
LFCSP (Paddle Soldered)
θ
JA
112
30.4
Unit
°C/W
°C/W
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
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