SYS81000FKXI-85 datasheet, PDF

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SYS81000FKXI-85: DescriptionSRAM Module, 1MX8, 85ns, CMOS, 0.600 INCH, LOW PROFILE, PLASTIC, DIP-36; Categorystorage storage; File Size113KB，7 Pages; ManufacturerMOSA; Websitehttp://www.mosanalog.com

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SYS81000FKXI-85 Overview

SRAM Module, 1MX8, 85ns, CMOS, 0.600 INCH, LOW PROFILE, PLASTIC, DIP-36

SYS81000FKXI-85 Parametric

Parameter Name	Attribute value
Maker	MOSA
Parts packaging code	MODULE
package instruction	,
Contacts	36
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	85 ns
JESD-30 code	R-XDMA-T36
memory density	8388608 bit
Memory IC Type	SRAM MODULE
memory width	8
Number of functions	1
Number of terminals	36
word count	1048576 words
character code	1000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	1MX8
Package body material	UNSPECIFIED
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	THROUGH-HOLE
Terminal location	DUAL

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1M x 8 SRAM MODULE

SYS81000FKX - 70/85/10/12

11403 West Bernado Court, Suite 100, San Diego, CA 92127.

Tel No: (001) 858 674 2233, Fax No: (001) 858 674 2230

Issue 3.0 : February 2000

Features

•

Access Times of 70/85/100/120 ns.

36 Pin JEDEC standard Dual-In-Line package.

5 Volt Supply ± 10%.

Low Power Dissipation:

Average (min cycle)

565mW (max).

Standby (-L Part CMOS)

3mW (max).

Completely Static Operation.

Low Voltage V

Data Retention.

Directly TTL Compatible.

On-board Supply Decoupling Capacitors.

Description

The SYS81000FKX is a plastic 8 Mbit Static RAM

Module housed in a JEDEC standard 36 pin Dual

In-Line package organised as 1M x8.

The module utilises SRAM's housed in TSOP II

packages, and uses single sided surface mount

techniques, buried decoder and dual board

construction to achieve a very high density module.

Fast access times of 70 to 120ns are available. The

OE pin allows faster access times than address

access during a read cycle. Low voltage data

retention mode available ( -L Version only).

•

Block Diagram

A0~A18

D0~D7

Pin Definition

Vcc

GND

TOP VIEW

A19

A18

A17

A16

GND

Vcc

A15

A14

A13

A12

A11

A10

512K x 8

SRAM

512K x 8

SRAM

A19

Decoder

Pin Functions

Address Inputs

Data Input/Output

Chip Select

Write Enable

Output Enable

Power (+5V)

Ground

A0 ~ A19

D0 ~ D7

GND

Package Details

Plastic 36 pin 0.6" Jedec DIP

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