204pin DDR3L SDRAM SODIMM
DDR3L SDRAM
Unbuffered SODIMMs
Based on 2Gb E-die
HMT325S6EFR8A
HMT351S6EFR8A
*SK hynix reserves the right to change products or specifications without notice.
Rev. 1.2 / Sep. 2013
1
Description
SK hynix Unbuffered DDR3L SDRAM DIMMs (Unbuffered Double Data Rate Synchronous DRAM Dual In-
Line Memory Modules) are low power, high-speed operation memory modules that use DDR3L SDRAM
devices. These Unbuffered DDR3L SDRAM DIMMs are intended for use as main memory when installed in
systems such as mobile personal computers.
Features
• Power Supply: VDD=1.35V (1.283V to 1.45V)
• VDDQ = 1.35V (1.283V to 1.45V)
• VDDSPD=3.0V to 3.6V
•
Backward Compatible with 1.5V DDR3 Memory module
• 8 internal banks
• Data transfer rates:PC3-12800, PC3-10600, PC3-8500
• Bi-directional Differential Data Strobe
• 8 bit pre-fetch
• Burst Length (BL) switch on-the-fly: BL 8 or BC (Burst Chop) 4
• On Die Termination (ODT) supported
• This product is in Compliance with the RoHS directive
Ordering Information
Part Number
HMT325S6EFR8A-G7/H9/PB
HMT351S6EFR8A-G7/H9/PB
Density
2GB
4GB
Organization
256Mx64
512Mx64
Component Composition
256Mx8(H5TC2G83EFR)*8
256Mx8(H5TC2G83EFR)*16
# of
ranks
1
2
Rev. 1.2 /Sep. 2013
3
Pin Descriptions
Pin Name
CK[1:0]
CK[1:0]
CKE[1:0]
RAS
CAS
WE
S[1:0]
A[9:0],A11,
A[15:13]
A10/AP
A12/BC
BA[2:0]
ODT[1:0]
SCL
SDA
SA[1:0]
Description
Clock Input, positive line
Clock Input, negative line
Clock Enables
Row Address Strobe
Column Address Strobe
Write Enable
Chip Selects
Address Inputs
Address Input/Autoprecharge
Address Input/Burst chop
SDRAM Bank Addresses
On Die Termination Inputs
Serial Presence Detect (SPD)
Clock Input
SPD Data Input/Output
SPD Address Inputs
Num
ber
2
2
2
1
1
1
2
14
1
1
3
2
1
1
2
V
REFDQ
V
REFCA
V
TT
V
DDSPD
NC
Input/Output Reference
Termination Voltage
SPD Power
Reserved for future use
1
1
2
1
2
Total: 204
Pin Name
DQ[63:0]
DM[7:0]
DQS[7:0]
DQS[7:0]
EVENT
TEST
RESET
V
DD
V
SS
Description
Data Input/Output
Data Masks
Data strobes
Data strobes, negative line
Temperature event pin
Logic Analyzer specific test pin (No
connect on SODIMM)
Reset Pin
Core and I/O Power
Ground
Num
ber
64
8
8
8
1
1
1
18
52
Rev. 1.2 /Sep. 2013
5
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