240pin Load Reduced DDR3(L) SDRAM DIMM
DDR3(L) SDRAM Load Reduced DIMM
Based on 4Gb A-die
HMT84GL7AMR4A
HMT84GL7AMR4C
*SK hynix reserves the right to change products or specifications without notice.
Rev. 0.3 / Jul. 2013
1
Revision History
Revision No.
0.1
0.2
History
Initial Release
IDD Specification Update &
Changed module maximum thickness
to reflect the measured maximum
IDD Update
(Montage 1.5V 1866Mbps)
Draft Date
Mar.2013
Jun.2013
Remark
0.3
Jul.2013
Rev. 0.3 / Jul. 2013
2
Description
SK hynix Load Reduced DDR3(L) SDRAM DIMMs are low power, high-speed operation memory modules
that use SK hynix DDR3(L) SDRAM devices. These Load Reduced DIMMs are intended for use as main
memory when installed in systems such as servers and workstations.
Features
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240 pin Load Reduced DDR3(L) DRAM Dual In-Line Memory Module
Buffer performance by LRDIMM presenting less load to system
Compatible with RDIMM systems with appropriate BIOS changes
Backward Compatible with 1.5V DDR3 Memory Module
(1.35V could not support the upper 1.5V speed)
Built with 4Gb DDR3 SDRAM 78ball
Data transfer rates: Up to PC3L-12800 / PC3-14900
JEDEC standard Double Data Rate3 Synchronous DRAMs(DDR3 SDRAMs) with 1.5V nominal
JEDEC standard Double Data Rate3L Synchronous DRAMs(DDR3L SDRAMs) with 1.35V nominal
Functionality and operations are same with DDR3 & DDR3L about same speed bin
Host interface and MB(Memory Buffer) component industry standard compliant
MB provides “address multiplication” to generate additional chips selects
Address mirroring
ODT (On-Die Termination)
133.35 x 30.35 mm form factor
Full DIMM Heat Spreader
This product is in compliance with the RoHS directive.
Ordering Information
# of
ranks
MB
FDHS
Vendor version
Montage
DDP 2Gx4(H5TC8G43AMR)*36
Inphi
32GB
HMT84GL7AMR4C
-H9/PB/RD
4Gx72
DDP 2Gx4(H5TQ8G43AMR)*36
Inphi
GS02B
4
Montage
C1
GS02B
O
30.35mm
C1
Height
Part Number
Density Organization
Component Composition
HMT84GL7AMR4A
-H9/PB
* In order to uninstall FDHS, please contact sales administrator
Rev. 0.3 / Jul. 2013
3
Key Parameters
MT/s
DDR3-1066
DDR3-1333
DDR3-1600
DDR3-1866
Grade
-G7
-H9
-PB
-Rd
tCK
(ns)
1.875
1.5
1.25
1.07
CAS
Latency
(tCK)
7
9
11
13
tRCD
(ns)
13.125
tRP
(ns)
13.125
tRAS
(ns)
37.5
36
35
34
tRC
(ns)
50.625
49.5
(49.125)*
48.75
(48.125)*
47.91
(48.125)*
CL-tRCD-tRP
7-7-7
9-9-9
11-11-11
13-13-13
13.5
13.5
(13.125)* (13.125)*
13.75
13.75
(13.125)* (13.125)*
13.91
13.91
(13.125)* (13.125)*
*
SK hynix DRAM devices support optional downbinning to CL11, CL9 and CL7. SPD setting is programmed to match.
Speed Grade
Frequency [MHz]
Grade
CL6
-G7
-H9
-PB
-RD
800
800
800
800
CL7
1066
1066
1066
1066
CL8
1066
1066
1066
1066
1333
1333
1333
1333
1333
1333
1600
1600
1866
CL9
CL10
CL11
CL12
CL13
Remark
Address Table
32GB(4Rx4)
Refresh Method
Row Address
Column Address
Bank Address
Page Size
8K/64ms
A0-A15
A0-A9,A11
BA0-BA2
1KB
Rev. 0.3 / Jul. 2013
4
Pin Descriptions
Pin Name
CK0
CK0
CK1
CK1
CKE[1:0]
Description
Clock Input, positive line
Clock Input, negative line
Clock Input, positive line
Clock Input, negative line
Clock Enables
Clock Enables
On Die Termination
CKE[3:2],
ODT[1], TEST Memory bus tool (Not Con-
nected and Not Useable on
DIMMs)
RAS
CAS
Row Address Strobe
Column Address Strobe
2
DQS[8:0]
Data strobes
9
Num
ber
1
1
1
1
2
Pin Name
Par_In
Err_Out
ODT[0]
DQ[63:0]
CB[7:0]
Description
Parity bit for the Address and Con-
trol bus
Parity error found on the Address
and Control bus
On Die Termination Inputs
Data Input/Output
Data check bits Input/Output
Num
ber
1
1
1
64
8
1
1
DQS[8:0]
DM[8:0]/
DQS[17:9],
TDQS[17:9]
DQS[17:9],
TDQS[17:9]
EVENT
TEST
RESET
V
DD
V
SS
V
REFDQ
V
REFCA
V
TT
V
DDSPD
Data strobes, negative line
Data Masks / Data strobes,
Termination data strobes
Data Masks / Data strobes,
Termination data strobes
Reserved for optional hardware
temperature sensing
Memory bus test tool (Not Con-
nected and Not Usable on DIMMs)
Register and SDRAM control pin
Power Supply
Ground
Reference Voltage for DQ
Reference Voltage for CA
Termination Voltage
SPD Power
9
9
WE
S[1:0]
S[3:2], A17,
A16
A[9:0],A11,
A[15:13]
A10/AP
A12/BC
BA[2:0]
SCL
SDA
SA[2:0]
Write Enable
Chip Selects
Chip Selects
Address Inputs
Address Inputs
Address Input/Autoprecharge
Address Input/Burst chop
SDRAM Bank Addresses
Serial Presence Detect (SPD)
Clock Input
SPD Data Input/Output
SPD Address Inputs
1
2
2
14
1
1
3
1
1
3
9
1
1
1
22
59
1
1
4
1
Rev. 0.3 / Jul. 2013
5
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