Integrated
Circuit
Systems, Inc.
ICS9250-22
Frequency Generator for P IV
Recommended Application:
P IV Chipset Support
Output Features:
•
4 Differential CPU Clock Pairs @ 3.3V
•
2 - 3V MREF clocks for memory reference seeds,
(separate single ended but 180 degrees out of phase)
•
4 - 66MHz reference output
•
10 - 3V 33MHz PCI clocks
•
2 - 48MHz clocks
•
2 - 14.318 reference output
Features:
•
Support power management: Power Down Mode
•
Supports Spread Spectrum modulation: 0 to -0.5% down
spread.
•
Uses external 14.318MHz crystal
•
Select logic for Differential Swing Control, Test mode,
Tristate, Power down, Spread Spectrum, limited
frequency select, selective clock enable.
•
External resistor for current reference
•
FS pins for frequency select
Key Specifications:
•
3V66 Output jitter <300ps
•
CPU Output Jitter <200ps
•
MREF Output jitter <250ps
Pin Configuration
GND
MULTSEL0/REF
MULTSEL1/REF
VDDREF
X1
X2
GNDREF
PCICLK0
PCICLK1
VDDPCI
PCICLK2
PCICLK3
GNDPCI
PCICLK4
PCICLK5
VDDPCI
PCICLK6
PCICLK7
GNDPCI
PCICLK8
PCICLK9
VDDPCI
SEL100/133
GND48
FS0/48MHz
FS1/48MHz
VDD48
PD#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDMREF
3VMREF
3VMREF_B
GNDMREF
SPREAD#
CPUCLKT3
CPUCLKC3
VDDCPU
CPUCLKT2
CPUCLKC2
GNDCPU
CPUCLKT1
CPUCLKC1
VDDCPU
CPUCLKT0
CPUCLKC0
GNDCPU
I REF
VDDA
GNDA
VDD3V66
3V66-3
3V66-2
GND3V66
GND3V66
3V66-1
3V66-0
VDD3V66
56-Pin 300mil SSOP & TSSOP
Functionality
SEL133/
100
0
0
0
0
1
1
1
1
FS0
0
0
1
1
0
0
1
1
FS1
0
1
0
1
0
1
0
1
Function
Active 100MHz
(Reserved)
(Reserved)
Tristate all outputs
Active 133MHz
(Reserved)
(Reserved)
Test Mode
3VMREF
DIVDER
Block Diagram
PLL2
2
ICS9250-22
48MHz
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
2
REF
CPU
DIVDER
4
4
CPUCLKT (3:0)
CPUCLKC (3:0)
3VMREF
3VMREF_B
Power Groups
VDDREF, GNDREF= REF, X1, X2
VDDPCI, GNDPCI = PCICLK
VDD48, GND48 = 48MHz, PLL2
VDD3V66, GND3V66=3V66
VDDCPU, GNDCPU = CPUCLK
VDDMREF, GNDMREF=3VMREF, 3VMREF_B
VDDA=VDD (core supply voltage 3.3V)
GNDA=Ground for core supply
9250-22 Rev A 8/25/00
Third party brands and names are the property of their respective owners.
PD#
SPREAD#
MULTSEL (1:0)
SEL100/133
FS(1:0)
Control
Logic
Config.
Reg.
3V66
DIVDER
4
PCI
DIVDER
10
PCICLK (9:0)
3V66 (3:0)
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9250-22
General Description
The
ICS9250-22
is a single chip clock solution.
Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9250-22 employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and temperature variations.
Pin Configuration
PIN NUMBER
1, 7, 13, 19, 24, 32,
33, 37, 40, 46, 53
3, 2
4, 10, 16, 22, 27, 29,
36, 38, 43, 49, 56
5
6
21, 20, 18, 17, 15,
14, 12, 11, 9, 8
23
26, 25
28
35, 34, 31, 30
39
51, 48, 45, 42
50, 47, 44, 41
PIN NAME
GND
REF/MULTSEL (1:0)
VDD
X1
X2
PCICLK (9:0)
SEL100/133
FS (1:0)
48MHz
PD#
3V66 (3:0)
I REF
CPUCLKT (3:0)
CPUCLKC (3:0)
TYPE
PWR
IN
PWR
X2 Crystal Input
DESCRIPTION
Ground pins for 3.3V supply
MULTSEL0 and MULTSEL1 inputs are sensed on power-up and
then internally latched prior to the pin being used for output on 3V
14.318MHz clocks.
3.3V power supply
14.318MHz Crystal input
X1 Crystal Output 14.318MHz Crystal output
OUT
IN
IN
OUT
IN
OUT
OUT
OUT
OUT
PCI clock outputs
CPU Frequency Select. Low=100MHz, High=133MHz
Frequency select pins
48MHz clock output
Invokes power-down mode. Active Low.
66MHz reference clocks
This pin establishes the reference current for the CPUCLK pairs.
This pin takes a fixed precision resistor tied to ground in order to
establish the appropriate current.
"True" clocks of differential pair CPU outputs. These are current
outputs and external resistors are required for voltage bias.
"Complementory" clocks of differential pair CPU outputs. These
are current outputs and external resistors are required for
voltage bias.
Invokes Spread Spectrum functionality on the Differential host
clocks, MRef/MRef_b clocks, 66MHz clocks, and 33MHz PCI
clocks. Active Low
3V reference to memory clock driver
(out of phase with 3Vmref)
3V reference to memory clock driver
52
54
55
SPREAD#
3VMREF_B
3VMREF
IN
OUT
OUT
Third party brands and names are the property of their respective owners.
2
ICS9250-22
Truth Table
SEL
133/100
0
0
0
0
1
1
1
1
FS0
0
0
1
1
0
0
1
1
FS1
0
1
0
1
0
1
0
1
CPU
100MHz
N/A
N/A
Tristate
133MHz
N/A
N/A
TCLK/2
MRef
50MHz
N/A
N/A
Tristate
66MHz
N/A
N/A
TCLK/4
3V66
66MHz
N/A
N/A
Tristate
66MHz
N/A
N/A
TCLK
PCI
33MHz
N/A
N/A
Tristate
33MHz
N/A
N/A
TCLK/6
48MHz
48MHz
N/A
N/A
Tristate
48MHz
N/A
N/A
REF
14.318MHz
N/A
N/A
Tristate
14.318MHz
N/A
N/A
TCLK
Group Offset Limits
Group
CPU to 3V66
CPU to PCI
3V66 to PCI
1.5 - 3.5ns
3V66 leads
30pF
1.5V
Offset
No Requirement
Measurement Loads
(lumped)
Measure Points
Third party brands and names are the property of their respective owners.
3
ICS9250-22
CPUCLK Buffer Configuration
Conditions
Iout
Vdd = nominal (3.30V)
Configuration
All combinations of M0,
M1 and Rr shown in
table below
All combinations of M0,
M1 and Rr shown in
table below
Load
Nominal test load for
given configuration
Nominal test load for
given configuration
Min
-7%
I
nominal
Max
+7%
I
nominal
Iout
Vdd = 3.30 ± 5%
-12%
I
nominal +12%
I
nominal
CPUCLK Swing Select Functions
MULTSEL0
0
0
0
0
1
1
1
1
MULTSEL1
0
0
1
1
0
0
1
1
Board Target
Trace/Term Z
60 ohms
50 ohms
60 ohms
50 ohms
60 ohms
50 ohms
60 ohms
50 ohms
Reference R,
Iref=
Vdd/(3*Rr)
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Output
Current
Ioh = 5*Iref
Ioh = 5*Iref
Ioh = 6*Iref
Ioh = 6*Iref
Ioh = 4*Iref
Ioh = 4*Iref
Ioh = 7*Iref
Ioh = 7*Iref
Voh @ Z,
Iref=2.32mA
0.71V @ 60
0.59V @ 50
0.85V /2 60
0.71V @ 50
0.56V @ 60
0.47V @ 50
0.99V @ 60
0.82V @ 50
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
Ioh = 5*Iref
Ioh = 5*Iref
Ioh = 6*Iref
Ioh = 6*Iref
Ioh = 4*Iref
Ioh = 4*Iref
Ioh = 7*Iref
Ioh = 7*Iref
0.75V @ 30
0.62V @ 20
0.90V @ 30
0.75V @ 20
0.60 @ 20
0.5V @ 20
1.05V @ 30
0.84V @ 20
Third party brands and names are the property of their respective owners.
4
ICS9250-22
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient Operating Temperature . . . . . . . . . . . . .
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .
5.5 V
GND 0.5 V to V
DD
+0.5 V
0°C to +70°C
115°C
65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70C; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
Input High Voltage
V
IH
Input Low Voltage
V
IL
Input High Current
I
IH
V
IN
= V
DD
V
IN
= 0 V; Inputs with no pull-up resistors
I
IL1
Input Low Current
V
IN
= 0 V; Inputs with pull-up resistors
I
IL2
Operating Supply
I
DD3.3OP
C
L
= 0 pF; Select @ 100 MHz
Current
I
DD3.3PD
C
L
= 0 pF; Input address to VDD or GND
Powerdown Current
V
DD
= 3.3 V
Input Frequency
F
i
Pin Inductance
L
pin
Logic Inputs
C
IN
Output pin capacitance
C
OUT
Input Capacitance
1
X1 & X2 pins
C
INX
Transition time
1
Settling time
1
Clk Stabilization
1
Delay
1
1
MIN
2
V
SS
-0.3
-5
-5
-200
TYP
MAX
V
DD
+0.3
0.8
5
UNITS
V
V
µA
µA
mA
mA
MHz
nH
pF
pF
pF
ms
ms
ms
ns
ns
130
35
14.318
250
60
7
5
6
45
3
3
3
10
10
27
T
trans
T
s
T
STAB
t
PZH
,t
PZL
t
PHZ
,t
PLZ
To 1st crossing of target frequency
From 1st crossing to 1% target frequency
From V
DD
= 3.3 V to 1% target frequency
Output enable delay (all outputs)
Output disable delay (all outputs)
1
1
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
5
stm32/stm8
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