Description
The H5TC8G43MMR-xxA and H5TC8G83MMR-xxA are a 8Gb low power Double Data Rate III (DDR3L) Syn-
chronous DRAM, ideally suited for the main memory applications which requires large memory density,
high bandwidth and low power operation at 1.35V. DDR3L SDRAM provides backward compatibility with
the 1.5V DDR3 based environment without any changes. (Please refer to the SPD information for details.)
SK hynix 8Gb DDR3L SDRAMs offer fully synchronous operations referenced to both rising and falling
edges of the clock. While all addresses and control inputs are latched on the rising edges of the clock (fall-
ing edges of the clock), data, data strobes and write data masks inputs are sampled on both rising and
falling edges of it. The data paths are internally pipelined and 8-bit prefetched to achieve very high band-
width.
Device Features and Ordering Information
FEATURES
• VDD=VDDQ=1.35V + 0.100 / - 0.067V
• Fully differential clock inputs (CK, CK) operation
• Differential Data Strobe (DQS, DQS)
• Average Refresh Cycle (Tcase of
0
o
C~ 95
o
C)
- 7.8 µs at
0
o
C ~ 85
o
C
- 3.9
µs at 85
o
C ~ 95
o
C
• On chip DLL align DQ, DQS and DQS transition with CK
• JEDEC standard 78ball FBGA(x4/x8)
transition
• Driver strength selected by EMRS
• DM masks write data-in at the both rising and falling
• Dynamic On Die Termination supported
edges of the data strobe
• Asynchronous RESET pin supported
• All addresses and control inputs except data,
• ZQ calibration supported
data strobes and data masks latched on the
rising edges of the clock
• TDQS (Termination Data Strobe) supported (x8 only)
• Programmable CAS latency 6, 7, 8, 9, 10 and 11
supported
• Programmable additive latency 0, CL-1, and CL-2
supported
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
• BL switch on the fly
• 8banks
• Write Levelization supported
• 8 bit pre-fetch
• This product in compliance with the RoHS directive.
Rev. 1.1 / Apr. 2013
3
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