FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-50216-1E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
16M (× 8/×16) FLASH MEMORY &
2M (× 8/×16) STATIC RAM
MB84VD2108XEA
-70/85
/MB84VD2109XEA
-70/85
s
FEATURES
• Power Supply Voltage of 2.7 to 3.3 V
• High Performance
70 ns maximum access time
• Operating Temperature
–40 to +85°C
• Package 56-ball FBGA, 56-pin TSOP
s
PRODUCT LINE UP
Flash Memory
-70
Power Supply Voltage (V)
Max Address Access Time (ns)
Max CE Access Time (ns)
Max OE Access Time (ns)
V
CC
f*
=
3.0 V
70
70
30
+0.3 V
–0.3 V
SRAM
-85
85
85
35
-70
V
CC
s*
=
3.0 V
70
70
35
+0.3 V
–0.3 V
-85
85
85
45
* : Both V
CC
f and V
CC
s must be in recommend operation range when either part is being accessed.
s
PACKAGES
56-ball plastic FBGA
56-pin plastic TSOP
(BGA-56P-M01)
(FPT-56P-M04)
Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
MB84VD2108XEA
-70/85
/MB84VD2109XEA
-70/85
FLASH MEMORY
•
Simultaneous Read/Write Operations (dual bank)
Miltiple devices available with different bank sizes (refer to “s PIN DESCRIPTION”)
Host system can program or erase in one bank, then immediately and simultaneously read from the other bank
Zero latency between read and write operations
Read-while-erase
Read-while-program
• Minimum 100,000 Write/Erase Cycles
•
Sector Erase Architecture
Eight 4 K words and thirty one 32 K words.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
•
Boot Code Sector Architecture
MB84VD2108XEA: Top sector
MB84VD2109XEA: Bottom sector
•
Embedded Erase
TM
Algorithms
Automatically pre-programs and erases the chip or any sector
•
Embedded Program
TM
Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
•
Ready-Busy Output (RY/BY)
Hardware method for detection of program or erase cycle completion
•
Automatic Sleep Mode
When addresses remain stable, automatically switch themselves to low power mode.
•
Low V
CC
Write Inhibit
≤
2.5 V
•
Hidden ROM (Hi-ROM) Region
64K byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
•
WP/ACC Input Pin
At V
IL
, allows protection of boot sectors, regardless of sector protection/unprotection status
(MB84VD2108XEA:SA37,SA38 MB84VD2109XEA:SA0,SA1)
At V
IH
, allows removal of boot sector protection
At V
ACC
, program time will reduse by 40%.
•
Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
• Please refer to “MBM29DL16XTE/BE” datasheet in detailed function
SRAM
•
Power Dissipation
Operating : 50 mA Max
Standby : 7
µA
Max
• Power Down Features Using CE1s and CE2s
• Data Retention Supply Voltage: 1.5 V to 3.3 V
• CE1s and CE2s Chip Select
• Byte Data Control: LBs (DQ
7
-DQ
0
), UBs (DQ
15
-DQ
8
)
2
MB84VD2108XEA
-70/85
/MB84VD2109XEA
-70/85
s
PIN DESCRIPTION
Pin
A
0
to A
16
A
–1
, A
17
to A
19
SA
DQ
0
to DQ
15
CEf
CE1s
CE2s
OE
WE
RY/BY
UBs
LBs
CIOf
CIOs
RESET
WP/ACC
N.C.
V
SS
V
CC
f
V
CC
s
Address Input (Common)
Address Input (Flash)
Address Input (SRAM)
Data Input/Output (Common)
Chip Enable (Flash)
Chip Enable (SRAM)
Chip Enable (SRAM)
Output Enable (Common)
Write Enable (Common)
Ready/Busy Outputs (Flash) Open Drain Output
Upper Byte Control (SRAM)
Lower Byte Control (SRAM)
I/O Configuration (Flash)
CIOf = V
CC
f is Word mode (×16), CIOf = V
SS
is Byte mode (×8)
I/O Configuration (SRAM)
CIOs = V
CC
s is Word mode (×16), CIOs = V
SS
is Byte mode (×8)
Hardware Reset Pin/Sector Protection Unlock (Flash)
Write Protect / Acceleration (Flash)
No Internal Connection
Device Ground (Common)
Device Power Supply (Flash)
Device Power Supply (SRAM)
Function
Input/Output
I
I
I
I/O
I
I
I
I
I
O
I
I
I
I
I
I
—
Power
Power
Power
5
京公网安备 11010802033920号
EEWORLD
