Z9305/Z9309
Zero Delay Clock Buffer
Preliminary
Product Features
•
•
•
•
•
•
•
•
Zero input-output propagation delay
Output-output skew less than 250 ps
Device-device skew less than 700 ps
One input drives nine outputs, grouped as 4/4/1
(Z9309)
10 MHz to 150 MHz operating range, compatible
with CPU and PCI bus frequencies
Less than 200 ps cycle-cycle jitter, compatible with
Pentium and Pentium Pro –based systems
Test Mode to bypass PLL (Z9309)
Available in space-saving 16 pin 150-mil SOIC and
TSSOP package (Z9309), and 8 pin 150 Mil SOIC
package (Z9305)
Product Description
The Z9309 is a low cost 3.3V zero delay buffer
designed to distribute high speed clocks in PC system
devices and SDRAM modules and is available in a 16-
pin SOIC or TSSOP package. The Z9305 is an 8-pin
version of the Z9309 and it accepts one reference input
and drives out five low skew clocks. The devices have
an on-chip PLL which locks to an input clock on the
REF pin. The PLL feedback is on-chip and is obtained
from the CLKOUT pad.
The Z9309 has two banks of four outputs each, which
can be controlled by the Select inputs as shown in the
Table 1. If all output clocks are not required, Bank B can
be tri-stated. The select inputs also allow the input clock
to be directly applied to the output for chip and system
testing purposes.
The Z9305 and Z9309 PLLs enter a Power Down mode
when there are no rising edges on the REF input. In this
state, the outputs are tri-stated and the PLL is turned
off, resulting in less than 50 uA of current draw. The
Z9309 PLL shuts down in one additional case as shown
in Table 1.
Multiple Z9305 and Z9309 devices can accept the same
input clock and distribute it. In this case, the skew
between the outputs of two devices is guaranteed to be
less than 700 ps.
All outputs have less than 200 ps of cycle-cycle jitter.
The input to output propagation delay is guaranteed to
be less than 350 ps, and the output to output skew is
guaranteed to be less than 250 ps.
Block Diagram (Z9305)
REF
PLL
CLKOUT
CLK1
CLK2
CLK3
CLK4
Block Diagram (Z9309)
PLL
CLKOUT
CLKA1
CLKA2
CLKA3
S2
S1
Select Input
Decoding
CLKA4
REF
CONNECTION DIAGRAM
CLKB2
CLKB3
CLKB4
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Z9309
CLKB1
REF
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLKOUT
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
REF
CLK2
CLK1
GND
1
2
3
4
8
7
6
5
CLKOUT
CLK4
VDD
CLK3
Rev.1.0
11/4/1999
Page 1 of 9
Z9305
Z9305/Z9309
Zero Delay Clock Buffer
Preliminary
Pin Description (Z9305)
PIN No.
1
2
3
4
5
6
7
8
Pin Name
(1)
REF
(1)
CLK2
(1)
CLK1(
GND
(1)
CLK3
VDD
(1)
CLK4
(1)
CLKOUT
I/O
I
O
O
I
O
O
O
Description
Input reference frequency, 5.0 V tolerant input.
Buffered Clock Output
Buffered Clock Output
Ground
Buffered Clock Output
3.3V supply
Buffered Clock Output
Buffered clock output, internal feedback on this pin.
Pin Description (Z9309)
PIN No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
(1)
REF
(1)
CLKA1
(1)
CLKA2
VDD
GND
(1)
CLKB1
(1)
CLKB2
(2)
S2
(2)
S1
(1)
CLKB3
(1)
CLKB4
GND
VDD
(1)
CLKA3
(1)
CLKA4
(1)
CLKOUT
I/O
I
O
O
I
I
O
O
I
I
O
O
Description
Input reference frequency, 5.0 V tolerant input.
Clock Output, Bank A.
Clock Output, Bank A.
3.3 V Supply
Ground
Clock Output, Bank B.
Clock Output, Bank B.
Select Input pin, bit 2.
Select Input pin, bit 1
Clock Output, Bank B.
Clock Output, Bank B.
Ground
3.3V supply
Clock Output, Bank A.
Clock Output, Bank A.
Buffered output, internal feedback on this pin.
O
O
O
Note 1:
Includes weak pull down.
Note 2:
Includes weak pull up.
Z9309 Select Input Functionality
S2
0
0
1
1
S1
0
1
0
1
CLKA1-A4
Tri-State
Driven
Driven
Driven
CLKB1-B4
Tri-State
Tri-State
Driven
Driven
CLK-OUT
Driven
Driven
Driven
Driven
Table 1
[1]
Output Source
PLL
PLL
REF
PLL
PLL Shut-down
N
N
Y
N
Note 1: This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the
reference and output.s.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.0
11/4/1999
Page 2 of 9
Z9305/Z9309
Zero Delay Clock Buffer
Preliminary
REF, Input T0 CLKA/CLKB Delay vs. Loading Difference Between CLKOUT & CLKA/CLKB
Pins
1500
Ref - Input to CLKA/CLKB Delay (ps)
1000
500
0
-30
-500
-1000
-1500
Output Load Difference: CLKOUT Load - CLKA/CLKB Load (PF)
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero Delay between the input and output. Since the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust the input-output delay. This is shown in the above graph.
For applications requiring zero input-output delay, all outputs including CLKOUT must be equally loaded. Even if
CLKOUT is not used, it must have a capacitive load equal to that on other outputs. If input to output delay adjustments
are required, use the above graph to calculate loading differences between the CLKOUT pin and other outputs.
For zero output-output skew, be sure to load all outputs equally.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev. 1.0
11/4/1999
Page 3 of 9
Z9305/Z9309
Zero Delay Clock Buffer
Preliminary
Maximum Ratings
Voltage Relative to VSS:
Voltage Relative to VDD:
Storage Temperature:
Operating Temperature:
Maximum Power Supply:
-0.3V
0.3V
0°C to + 125°C
0°C to +85°C
7V
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
DC Electrical Characteristics (Z9305/Z9309)
(VDD = 3.0 to 3.6 V, TA = 0°C to 85°C)
Characteristic
Input Low Voltage
Input Low Current
Input High Current
Output Low Voltage
(2)
(2)
(1)
(1)
Symbol
VIL
VIH
IIL
IIH
VOL
VOH
Ioz
Idd
Idd
Min
-
2.0
Typ
-
-
Max
0.8
50.0
±100
0.4
Units
Vdc
Vdc
µA
µA
V
V
µA
µA
mA
Conditions
-
VIN = 0V
VIN = VDD
IOL = 8 mA
IOH = - 8mA
S1 = S2 = GND
Ref = 0 MHz
Unload outputs, 66.66 MHz, Select inputs
at VDD or GND.
Input High Voltage
Output High Voltage
2.4
-
-
-
-
-
-
10
50
40
Tri-State leakage Current
Power Down Supply Current
Dynamic Supply Current
Notes:
1. REF and FBK inputs have a threshold voltage of V
DD
/2.
2.
Parameter is guaranteed by design and characterization. Not 100% tested in production. All parameters specified
with loaded outputs.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev.1.0
11/4/1999
Page 4 of 9
Z9305/Z9309
Zero Delay Clock Buffer
Preliminary
Switching Characteristics (Z9305/Z9309)
(VDD = 3.0 to 3.6 V, TA = 0°C to 85°C)
Characteristic
Output Period
Input Period
Duty Cycle (T
2
/T
1
)
Rise Time
Fall Time
(1)
(1)
Symbol
t
1
t
1
-
t
3
t
4
(1)
Min
10
10
45
Typ
Max
150
150
Units
MHz
MHz
%
nSec
nSec
pSec
pSec
pSec
pSec
ms
Conditions
30 pF load
30 pF load
Measured @ 1.4V
Measured between 0.8V & 2.0V, 15 pF
Load
Measured between 0.8V & 2.0V, 15 pF
Load
All output equally loaded
Measured at V
DD
/2
Measured at V
DD
/2 on FBK pins of
devices
Measured at 66.67 MHz, loaded
outputs, input Trise/Fall < 1 nS
Stable power supply, valid clocks
presented on REF pin.
50
-
55
1.5
1.5
(1)
Output to Output Skew
t
5
t
6
t
7
tj
(1)
-
-
-
-
-
0
0
-
250
+ 350
700
200
1.0
Delay, REF Rising Edge to
(1)
CLKOUT Rising Edge
Device to Device Skew
Cycle to Cycle Jitter
(1)
(1)
Maximum PLL Lock Time
tLOCK
Notes:
1. Parameter is guaranteed by design and characterization. Not 100% tested in production. All parameters specified
with loaded outputs.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035. TEL: 408-263-6300. FAX 408-263-6571
Rev. 1.0
11/4/1999
Page 5 of 9
Embedded System
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