Circuit Note
Circuits from the Lab™ reference circuits are engineered and
tested for quick and easy system integration to help solve today’s
analog, mixed-signal, and RF design challenges. For more
information and/or support, visit
www.analog.com/CN0187.
CN-0187
Devices Connected/Referenced
ADL5502
450 MHz to 6 GHz Crest Factor Detector
Differential/Single-Ended Input, Dual,
AD7266
Simultaneous Sampling, 2 MSPS, 12-Bit,
3-Channel SAR Analog-to-Digital Converter
Low Cost, Quad, CMOS, High Speed, Rail-to-
ADA4891-4
Rail Amplifier
150 mA, Low Quiescent Current, CMOS Linear
ADP121
Regulator in 5-Lead TSOT or 4-Ball WLCSP
Crest Factor, Peak, and RMS RF Power Measurement Circuit Optimized for
High Speed, Low Power, and Single 3.3 V Supply
EVALUATION AND DESIGN SUPPORT
Circuit Evaluation Boards
CN-0187 Circuit Evaluation Board (EVAL-CN0187-SDPZ)
System Demonstration Platform (EVAL-SDP-CB1Z)
Design and Integration Files
Schematics, Layout Files, Bill of Materials
CIRCUIT FUNCTION AND BENEFITS
The circuit shown in Figure 1 measures peak and rms power
at any RF frequency from 450 MHz to 6 GHz over a range of
approximately 45 dB. The measurement results are converted
to differential signals in order to eliminate noise and are
provided as digital codes at the output of a 12-bit SAR ADC
with serial interface and integrated reference. A simple two-
point calibration is performed in the digital domain.
+3.3V +3.3V
+3.3V
*SEE TEXT
8
220Ω
U2-B
442Ω
+3.3V
U2-A
AVDD DVDD
27Ω
VA1
U6
1000pF 0.1µF
C
FLTR
*
1
ENBL
FLTR
VPOS
U1
VRMS
7
PEAK
6
*
*
0.01µF
2
ADL5502
*
*
U3-B
220Ω
220Ω
+1.25V U2-D
10kΩ
0.47µF
10kΩ
0.47µF
220Ω
442Ω
+3.3V
U3-A
U3-A
27Ω
+2.5V
U2-C
AD7266
VDRIVE
VA2
D
CAP
A
0.01µF
RFIN
0.01µF
3
RFIN
COMM
4
CNTL
5
75Ω
CONTROL
(HIGH RESET;
LOW PEAK HOLD)
SDP
BOARD
AND
SUPPORT
CIRCUITS
CS
DOUTA
SCLK
NOTE: U2 AND U3 ARE ADA4891-4
+5.5V
VIN
1µF
EN
GND
VOUT
U5
+3.3V
1µF
27Ω
VB1
ADP121
220Ω
220Ω
U3-D
+1.25V U3-D
10kΩ
0.47µF
10kΩ
27Ω
+2.5V
D
CAP
B
U3-C
AGND
0.47µF
DGND
09569-001
VB2
Figure 1. High Speed, Low Power, Crest Factor, Peak, and RMS Power Measurement System (Simplified Schematic: All connections and Decoupling Not Shown)
Rev.0
Circuits from the Lab™ circuits from Analog Devices have been designed and built by Analog Devices
engineers. Standard engineering practices have been employed in the design and construction of
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room temperature. However, you are solely responsible for testing the circuit and determining its
suitability and applicability for your use and application. Accordingly, in no event shall Analog Devices
be liable for direct, indirect, special, incidental, consequential or punitive damages due to any cause
whatsoever connected to the use of any Circuits from the Lab circuits. (Continued on last page)
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©2011 Analog Devices, Inc. All rights reserved.
CN-0187
The
ADL5502
is a mean-responding (true rms) power detector
in combination with an envelope detector to accurately
determine the crest factor (CF) of a modulated signal. It can be
used in high frequency receiver and transmitter signal chains
from 450 MHz to 6 GHz with envelope bandwidths over 10 MHz.
The peak-hold function allows the capture of short peaks in the
envelope with lower sampling rate ADCs. Total current
consumption is only 3 mA @ 3 V.
The
ADA4891-4
is a high speed, quad, CMOS amplifier that
offers high performance at a low cost. Current consumption is
only 4.4 mA/amplifier at 3 V. The amplifier features true single-
supply capability, with an input voltage range that extends 300 mV
below the negative rail. The rail-to-rail output stage enables
the output to swing to within 50 mV of each rail, ensuring
maximum dynamic range. Low distortion and fast settling time
makes it ideal for this application.
The
AD7266
is a dual, 12-bit, high speed, low power, successive
approximation ADC that operates from a single 2.7 V to 5.25 V
power supply and features sampling rates up to 2 MSPS. The
device contains two ADCs, each preceded by a 3-channel
multiplexer, and a low noise, wide bandwidth track-and-hold
amplifier that can handle input frequencies in excess of 30 MHz.
Current consumption is only 3 mA at 3 V. It also contains an
internal 2.5 V reference.
The circuit operates on a single +3.3 V supply from the
ADP121,
a low quiescent current, low dropout, linear regulator
that operates from 2.3 V to 5.5 V and provides up to 150 mA
of output current. The low 135 mV dropout voltage at 150 mA
load improves efficiency and allows operation over a wide input
voltage range. The low 30 μA of quiescent current at full load
makes the ADP121 ideal for battery-operated portable equipment.
The ADP121 is available in output voltages ranging from 1.2 V
to 3.3 V. The parts are optimized for stable operation with small
1 μF ceramic output capacitors. The ADP121 delivers good
transient performance with minimal board area.
Short-circuit protection and thermal overload protection
circuits prevent damage in adverse conditions. The ADP121 is
available in tiny 5-lead TSOT and 4-ball, 0.4 mm pitch halide-
free WLCSP packages and utilizes the smallest footprint
solution to meet a variety of portable applications.
Circuit Note
The internal filter capacitor of the ADL5502 provides averaging
in the square domain but leaves some residual ac on the output.
Signals with high peak-to-average ratios, such as W-CDMA or
CDMA2000, can produce ac residual levels on the ADL5502
VRMS dc output. To reduce the effects of these low frequency
components in the waveforms, some additional filtering is
required. The internal square-domain filter capacitance of the
ADL5502 can be augmented by connecting a C
FLTR
capacitor
between Pin 1 (FLTR) and Pin 2 (VPOS). The ac residual can be
reduced further by adding capacitance to the VRMS output.
The combination of the internal 100 Ω output resistance and
the added output capacitance produces a low-pass filter to
reduce output ripple of the VRMS output (see the Selecting the
Square-Domain Filter and Output Low-Pass Filter section of the
ADL5502 data sheet for more details).
To measure the peak of a waveform, the control line (CNTL)
must be temporally set to a logic high (reset mode for >1 µs)
and then set back to a logic low (peak-hold mode). This allows
the ADL5502 to be initialized to a known state. When setting
the device to measure peak, peak-hold mode should be toggled
for a period in which the input rms power and crest factor (CF)
is not likely to change.
If the ADL5502 is in peak-hold mode and the CF changes from
high to low or the input power changes from high to low, a
faulty peak measurement is reported. The ADL5502 simply
keeps reporting the highest peak that occurred when the peak-
hold mode was activated and the input power or the CF was
high. Unless CNTL is reset, the PEAK output does not reflect
the new peak in the signal.
The ADL5502 is capable of sourcing a VRMS output current of
approximately 3 mA. The output current is sourced through the
on-chip, 100 Ω series resistor; therefore, any load resistor forms
a voltage divider with this on-chip resistance. It is
recommended that the ADL5502 VRMS output drive high
resistive loads to preserve output swing. If an application
requires driving a low resistance load (as well as in cases where
increasing the nominal conversion gain is desired), a buffering
circuit is necessary.
The PEAK output is designed to drive 2 pF loads. It is
recommended that the ADL5502 PEAK output drive low
capacitive loads to achieve a full output response time. The
effects of larger capacitive loads are particularly visible when
tracking envelopes during the falling transitions. When the
envelope is in a fall transition, the load capacitor discharges
through the on-chip load resistance of 1.9 kΩ. If the larger
capacitive load is unavoidable, the additional capacitance can be
counteracted by putting a shunt resistor to ground on the PEAK
output to allow for fast discharge. Such a shunt resistor also
makes the ADL5502 run higher current, and it should not be
lower than 500 Ω.
CIRCUIT DESCRIPTION
The RF signal being measured is applied to the ADL5502.
A single 75 Ω termination resistor at the RF input in parallel
with the input impedance of the ADL5502 provides a
broadband match of 50 Ω. More precise resistive or reactive
matches can be applied for narrow frequency band use (see
the RF Input Interfacing section of the ADL5502 data sheet).
Rev. 0| Page 2 of 7
Circuit Note
Typical measured performance characteristics of the circuit are
presented in Figure 2 through Figure 5.
10
CN-0187
2.0
1.8
1.6
1.4
OUTPUT (V)
450MHz
900MHz
1900MHz
2350MHz
2600MHz
1.2
1.0
0.8
0.6
0.4
0.2
0
0
0.2
0.4
0.6
1
OUTPUT (V)
0.1
450MHz
900MHz
1900MHz
2350MHz
2600MHz
09569-005
09569-053
0.8
1.0
–20
–15
–10
–5
0
INPUT (dBm)
5
10
15
09569-002
0.01
–25
INPUT (V rms)
Figure 2. Measured VRMS Output vs. Input Level (Log Scale), 450 MHz,
900 MHz, 1900 MHz, 2350 MHz, 2600 MHz, Supply +3.3 V
2.0
1.8
1.6
1.4
Figure 5. Measured PEAK Output vs. Input Level (Linear Scale), 450 MHz,
900 MHz, 1900 MHz, 2350 MHz, 2600 MHz, Supply +3.3 V
OUTPUT (V)
1.2
1.0
0.8
0.6
0.4
450MHz
900MHz
1900MHz
2350MHz
2600MHz
The turn-on time and pulse response is strongly influenced by
the size of the square-domain filter (C
FLTR
) and output shunt
capacitor connected to the VRMS output. Figure 6 (taken from
the ADL5502 data sheet) shows a plot of the output response to
an RF pulse on the RFIN pin, with a 0.1 μF output filter
capacitor and no square-domain filter capacitor (C
FLTR
). The
falling edge is particularly dependent on the output shunt
capacitance.
PULSED RFIN
400mV rms RF INPUT
0.2
09569-003
0
0
0.2
0.4
0.6
INPUT (V rms)
0.8
1.0
VRMS (250mV/DIV)
250mV rms
160mV rms
Figure 3. Measured VRMS Output vs. Input Level (Linear Scale), 450 MHz,
900 MHz, 1900 MHz, 2350 MHz, 2600 MHz, Supply +3.3 V
70mV rms
10
VRMS
1ms/DIV
1
Figure 6. Output Response to Various RF Input Pulse Levels, Supply3 V,
900 MHz Frequency, Square-Domain Filter Open, Output Filter 0.1 μF
OUTPUT (V)
0.1
450MHz
900MHz
1900MHz
2350MHz
2600MHz
–20
–15
–10
–5
INPUT (dBm)
0
5
10
15
Figure 4. Measured PEAK Output vs. Input Level (Log Scale), 450 MHz,
900 MHz, 1900 MHz, 2350 MHz, 2600 MHz, Supply +3.3 V
09569-004
0.01
–25
To improve the falling edge of the enable and pulse responses,
a resistor can be placed in parallel with the output shunt
capacitor. The added resistance helps to discharge the output
filter capacitor. Although this method reduces the power-off
time, the added load resistor also attenuates the output (see the
Output Drive Capability and Buffering section of the ADL5502
data sheet). Figure 7 (taken from the ADL5502 data sheet)
shows the improvement obtained by adding a parallel 1 kΩ
resistor.
Rev. 0| Page 3 of 7
CN-0187
PULSED RFIN
Circuit Note
Figure 8 and Figure 9 show plots of the VRMS and PEAK error
at 25°C, the temperature at which the ADL5502 is calibrated.
Note that the error is not zero; this is because the ADL5502
does not perfectly follow the ideal linear equation, even within
its operating region. The error at the calibration points is,
however, equal to zero by definition.
3
400mV rms RF INPUT
VRMS (250mV/DIV)
250mV rms
160mV rms
70mV rms
2
VRMS
1ms/DIV
09569-054
1
ERROR (dB)
Figure 7. Output Response to Various RF Input Pulse Levels, Supply 3 V,
900 MHz Frequency, Square-Domain Filter Open, Output Filter 0.1 μF
with Parallel 1 kΩ
0
450MHz
900MHz
1900MHz
2350MHz
2600MHz
–1
The RMS and PEAK outputs of the ADL5502 pass through
unity gain buffers that drive cross-coupled stages for converting
the single-ended outputs to differential signals. The internal
+2.5 V reference of the AD7266 (via the D
CAP
A and D
CAP
B pins)
passes through another unity gain buffer and a voltage divider.
This sets the common-mode voltage of the network to +1.25 V.
The AD7266 achieves simultaneous samples of the RMS and
PEAK outputs and transfers the data within a 1 µs response
time. The data is provided on a single serial data line. Because
slope and intercept vary from device to device, board-level
calibration must be performed to achieve high accuracy. In
general, calibration is performed by applying two input power
levels to the ADL5502 and measuring the corresponding output
voltages. The calibration points are generally chosen to be
within the linear operating range of the device. The best-fit line
is characterized by calculating the conversion gain (or slope)
and intercept using the following equations:
Gain
= (V
VRMS2
−
V
VRMS1
)/(V
IN2
−
V
IN1
)
Intercept
=
V
VRMS1
− (Gain ×
V
IN1
)
where:
V
IN
is the rms input voltage to RFIN.
V
VRMS
is the voltage output at VRMS.
Once gain and intercept are calculated, an equation can be
written that allows calculation of an (unknown) input power
based on the measured output voltage.
V
IN
= (V
VRMS
−
Intercept)/Gain
(3)
For an ideal (known) input power, the law conformance error of
the measured data can be calculated as
(1)
(2)
–2
–20
–15
–10
–5
INPUT (dBm)
0
5
10
15
Figure 8. Measured VRMS Linearity Error vs. Input Level, 450 MHz, 900 MHz,
1900 MHz, 2350 MHz, 2600 MHz, Supply +3.3 V
3
2
1
ERROR (dB)
0
450MHz
900MHz
1900MHz
2350MHz
2600MHz
–1
–2
–20
–15
–10
–5
INPUT (dBm)
0
5
10
15
Figure 9. Measured PEAK Linearity Error vs. Input Level, 450 MHz, 900 MHz,
1900 MHz, 2350 MHz, 2600 MHz, Supply +3.3 V
V
–
Intercept
ERROR
(dB)
=
20 × log
VRMS, MEASURED
Gain
×
V
IN, IDEAL
(4)
When the characteristics (slope and intercept) of the VRMS and
PEAK outputs are known, the calibration for the CF calculation
is complete. A three-stage process must be taken to measure
and calculate the crest factor of any waveform. First, the
unknown signal must be applied to the RF input, and the
corresponding VRMS level is measured. This level is indicated
in Figure 10 as
V
VRMS-UNKNOWN
. The RF input,
V
IN
, is calculated
using
V
VRMS-UNKNOWN
and Equation 3.
Rev. 0| Page 4 of 7
09569-009
–3
–25
09569-008
–3
–25
Circuit Note
3.0
CN-0187
OUTPUT (V)
PEAK OF
UNKNOWN WAVEFORM
CREST FACTOR (dB)
2.5
2.0
1.5
1.0
0.5
0
–0.5
450MHz
900MHz
1900MHz
2350MHz
2600MHz
V
PEAK-UNKNOWN
V
VRMS-UNKNOWN
V
PEAK-CW
3
VRMS OF
UNKNOWN WAVEFORM
(RESULT INDEPENDENT
OF WAVEFORM)
PEAK OF
CW, CF = 0dB
09569-057
2
1
0
V
IN
INPUT (V rms)
Figure 10. Procedure for Crest Factor Calculation
–15
–5
INPUT (dBm)
5
15
Next, the CW reference level of PEAK,
V
PEAK-CW
, is calculated
using
V
IN
(that is, the output voltage that would be seen if the
incoming waveform was a CW signal).
V
PEAK-CW
= (V
IN
Gain
PEAK
) +
Intercept
PEAK
(5)
Finally, the actual level of PEAK,
V
PEAK-UNKNOWN
, is measured and
the CF can be calculated as
CF
= 20 log
10
(V
PEAK-UNKNOWN
/V
PEAK-CW
)
(6)
where
V
PEAK-CW
is used as a reference point to compare
V
PEAK-UNKNOWN
. If both
V
PEAK
values are equal, then the CF is 0 dB,
as shown in Figure 11 with the CW signal (taken from the
ADL5502 data sheet). Across the dynamic range, the calculated
CF hovers about the 0 dB line. Likewise, for complex waveforms
of 3 dB, 6 dB, and 9 dB CFs, the calculations accurately hover
about the corresponding CF levels.
10
9
8
Figure 12. Measured Crest Factor of CW Signals vs. Input Level, 450 MHz,
900 MHz, 1900 MHz, 2350 MHz, 2600 MHz, Supply +3.3 V
The performance of this or any high speed circuit is highly
dependent on proper PCB layout. This includes, but is not
limited to, power supply bypassing, controlled impedance lines
(where required), component placement, signal routing, and
power and ground planes. (See
MT-031 Tutorial, MT-101 Tutorial,
and article,
A Practical Guide to High-Speed Printed-Circuit-
Board Layout,
for more detailed information regarding PCB
layout.)
A complete design support package for this circuit note can be
found at
http://www.analog.com/CN0187-DesignSupport.
COMMON VARIATIONS
8-TONE WAVEFORM, 9dB CF
CREST FACTOR (dB)
7
6
5
4
3
2
1
0
–1
–25
–20
4-TONE WAVEFORM, 6dB CF
For applications that require less RF detection range, the
AD8363
rms detector can be used. The AD8363 has a detection
range of 50 dB and operates at frequencies up to 6 GHz. For
non-rms detection applications, the
AD8317/AD8318/AD8319
or
ADL5513
can be used. These devices offer varying detection
ranges and have varying input frequency ranges up to 10 GHz
(see
CN-0150
for more details).
2-TONE WAVEFORM, 3dB CF
CIRCUIT EVALUATION AND TEST
CW, 0dB CF
–15
–10
–5
0
5
10
15
INPUT (dBm)
Figure 11. Reported Crest Factor of Various Waveforms
This circuit uses the EVAL-CN0187-SDPZ circuit board and the
EVAL-SDP-CB1Z System Demonstration Platform (SDP)
evaluation board. The two boards have 120-pin mating
connectors, allowing for the quick setup and evaluation of the
circuit’s performance. The EVAL-CN0187-SDPZ board contains
the circuit to be evaluated, as described in this note, and the
SDP evaluation board is used with the CN0187 evaluation
software to capture the data from the EVAL-CN0187-SDPZ
circuit board.
09569-058
Rev. 0| Page 5 of 7
09569-012
–1.0
–25
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