RAiO
RA8808
128x64 Driver
for Dot Matrix LCD
Specification
Version 1.0
March 26, 2009
RAiO Technology Inc.
©Copyright
RAiO Technology Inc. 2009
RAiO
TECHNOLOGY INC.
1/7
www.raio.com.tw
RA8808
Preliminary Version 1.0
128x64Driver for Dot Matrix LCD
1. General Description
The RA8808 is a LCD driver LSI with 128(Segment) x 64(Common) driver output for dot matrix liquid crystal
graphic display systems. This device consists of the display RAM,128-bit segment drivers, 64-bit common
drivers and decoder logic. It has the internal display RAM for storing the display data transferred from an 8-
bit 8080/6800 micro controller or 3-wire-SPI/IIC controller and generates the dot matrix liquid crystal driving
signals corresponding to stored data.
2. Features
Dot matrix LCD segment driver with 128
channel output, and common driver with 64
channel output.
Internal timing generator circuit for dynamic
display.
Selection of master/slave mode for combine
two RA8808 controller to support 256x64 dot
Matrix.
Applicable LCD common duty: 1/48, 1/64.
Support 6800/8080 8-bit parallel MPU interface.
Support 3-wires SPI and IIC serial MPU
interface.
Two 512 bytes (4096-bits) Display RAM
LCD driving voltage: 8V ~17V
Built-in 2X~4X Voltage Booster and Voltage
Follower
Power supply voltage: +2.7V ~ 5.5V
High voltage CMOS process
Bare gold bump chip available
3. Block Diagram
M CL FRM
DB7~0
RS
E
RW
CS1
CS2B
CS3
CS4B
PS
MODE
MS
DS
SHL
ADC
RSTB
RA
RB
Register
Block
Scan
Block
SEG
Drivers
SEG127~0
MPUIF
Block
512x8
Display RAM
A
512x8
Display RAM
B
Power Circuit &
Test
RC
Oscillator
COM
Drivers
COM63~0
CLK_OUT TEST[2~0]
VOUT
C[2:1]N
V[4:0]
V[4:0]A
C[3:1]P
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TECHNOLOGY INC.
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COM47
COM46
COM45
COM44
COM43
COM42
COM41
COM40
COM39
COM38
COM37
COM36
COM35
COM34
COM33
COM32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
P1
PT1
17
18
19
20
21
22
23
24
25
26
27
28
PT2
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
PT3
56
57
58
59
60
61
62
63
64
65
PT4
66
67
68
69
70
71
72
73
74
75
PT6
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
PT7
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
PT5
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
SEG41
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
X
Pin Name
5-1 MPU Interface
DB0~DB7
Preliminary Version 1.0
E
I/O
I/O
301
300
299
298
297
296
295
294
293
292
291
290
289
288
287
286
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
I
RAiO
TECHNOLOGY INC.
285
284
283
282
281
280
279
278
277
276
275
274
273
272
271
270
269
268
267
266
265
SEG127
SEG126
SEG125
SEG124
SEG123
SEG122
SEG121
SEG120
SEG119
SEG118
SEG117
SEG116
SEG115
SEG114
SEG113
SEG112
SEG111
SEG110
SEG109
SEG108
SEG107
RA8808
Top View
9166 x 1171
264
263
262
261
260
259
258
257
256
255
254
253
252
251
250
249
248
247
246
245
244
SEG106
SEG105
SEG104
SEG103
SEG102
SEG101
SEG100
SEG99
SEG98
SEG97
SEG96
SEG95
SEG94
SEG93
SEG92
SEG91
SEG90
SEG89
SEG88
SEG87
SEG86
DB0
DB1
DB2
DB3
DB4
DB5
Pin
DB7
DB6
Logo
RAiO
RA8808
Y
243
242
241
240
239
238
237
236
235
234
233
232
231
230
229
228
227
226
225
224
223
222
(0,0)
221
220
219
218
217
216
215
214
213
212
211
210
209
208
207
206
205
204
203
202
201
200
SEG85
SEG84
SEG83
SEG82
SEG81
SEG80
SEG79
SEG78
SEG77
SEG76
SEG75
SEG74
SEG73
SEG72
SEG71
SEG70
SEG69
SEG68
SEG67
SEG66
SEG65
SEG64
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
4. Pad Diagram
5. Pin Description
In IIC Interface :
These pins are used as the IIC device address input.
(SA[2:0])
In SPI Interface :
These pins are not used and must be connected to
high or low.
In IIC Interface :
This pin is not used and must be connected to low.
In SPI Interface :
This pin is used as Chip selection, active low. (ZCS)
In IIC Interface :
This pin is used as Bi-direction serial Data.(SDA)
In SPI Interface :
This pin is used as Bi-direction serial Data.(SDA)
In IIC Interface :
This pin is used as serial clock.(SCL)
In SPI Interface :
This pin is used as serial clock.(SCK)
In Parallel Mode :
Data Bus
These are data bus for data transfer between MPU(6800/8080) and RA8808.
In Serial Mode :
In Parallel Mode :
Enable or Read Control
When use 6800 series interface, this pin is used as Enable, active high.
When use 8080 series interface, this pin is used as data read, active low.
In Serial Mode :
This pin is not used and must be connected to low.
These pins are not used and must be connected to low.
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Description
Description
FRM
CL
M
CLK_OUT
VDD
MS
GND
VDD
MODE
PS
ADC
VDD
GND
CS4B
CS3
VDD
RSTB
RS
E
RW
GND
CS2B
CS1
VDD
GND
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VDD
VDD
VDD
VDDP
VDDP
VDDP
AVDD
AVDD
AVDD
AVDD
AVDD
AGND
AGND
AGND
AGND
AGND
GNDP
GNDP
GNDP
GND
GND
GND
VOUT
VOUT
VOUT
VOUT
C3P
C3P
C3P
C3P
C1N
C1N
C1N
C1N
C1P
C1P
C1P
C1P
C2N
C2N
C2N
C2N
C2P
C2P
C2P
C2P
V0A
V1A
V2A
V3A
V4A
V4
V4
V3
V3
V2
V2
V1
V1
V0
V0
VDD
VDD
VDD
SHL
GND
DS
GND
TEST0
TEST1
TEST2
RA
RB
M
CL
FRM
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
128x64Driver for Dot Matrix LCD
P2
www.raio.com.tw
RA8808
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
RA8808
Preliminary Version 1.0
128x64Driver for Dot Matrix LCD
RW
I
In Parallel Mode :
Read-Write Control or Write Control
When use 6800 series interface, this pin is used as data read/write control.
Active high for read and active low for write.
When use 8080 series interface, this pin is used as data write, active low.
In Serial Mode :
This pin is not used and must be connected to low.
In Parallel Mode :
Data or Instruction
RS = H
DB0~DB7 : Display RAM data
RS = L
DB0~DB7 : Instruction data
In Serial Mode :
This pin is not used and must be connected to low.
In Parallel Mode :
Chip selection for left side (Note 1)
In order to interface left side data for input or output, the terminals have to be
CS1 = H, CS2B = L.
In Serial Mode :
These pins are not used and must be connected to high or low.
In Parallel Mode :
Chip selection for right side (Note 1)
In order to interface right side data for input or output, the terminals have to
be
CS3 = H, CS4B = L.
In Serial Mode :
These pins are not used and must be connected to to high or low.
Reset Signal
When RSTB = L,
_ON/OFF register becomes set by 0. (display off)
_Display start line register becomes set by 0.(Z-address 0 set, display from
line 0)
After releasing reset, this condition can be changed only by instruction.
Parallel/Serial MPU Interface Selection
RS
I
CS1
CS2B
I
CS3
CS4B
I
RSTB
I
PS
I
PS
H
L
Parallel/Serial
Parallel
Serial
MPU Interface Selection(Combine with PS)
PS
H
H
L
L
MODE
H
L
H
L
MPU Interface
6800 series
8080 series
3-wire SPI
IIC
MODE
I
RAiO
TECHNOLOGY INC.
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RA8808
Preliminary Version 1.0
128x64Driver for Dot Matrix LCD
5-2 LCD Panel Interface
Pin Name
I/O
Description
LCD Segment Driver Output
Display RAM data 1 : On, Display RAM data 0 : Off
Relation of display RAM & M :
SEG0~
SEG127
O
M
L
L
H
H
Data
L
H
L
H
Output Level
V2
V0
V3
GND
Common Signal Output for LCD Driving
Relation of common signal & M :
COM0~
COM63
O
M
L
L
H
H
Common Signal
L
H
L
H
Output Level
V1
GND
V4
V0
M
I/O
Alternating Signal Input for LCD Driving.
The input/output selection is determined by MS.
Display Synchronous Signal
Display data is latched at rising time of the CL signal and increments the Z-
address counter at CL falling time. The input/output selection is determined
by MS.
Synchronous Control Signal
Presets the 6-bit Z counter and synchronizes the common signal with the
frame signal when the frame signal becomes high. The input/output
selection is determined by MS.
Master/Slave Mode Selection
MS
H
L
Master/Slave Mode
Master
Slave
CL
I/O
FRM
I/O
MS
I
When in Master mode, M, CL, FRM are output pins.
When in Slave mode, M, CL, FRM are input pins.
5-3 Clock
Pin Name
I/O
Description
In internal clock mode, this pin connects to external resistor for RC circuit.
In external clock mode, this pin is an input of external clock.
Internal Clock Mode
External Clock Mode
RA8808
RA
I
RA8808
RA
R
RB
50pF
RA
External Clock
RB
Open
RB
CLK_OUT
O
O
In internal clock mode, this pin connects to external resistor for RC circuit.
In external clock mode, this pin must keep floating.
Internal system clock output for cascade application or others for user.
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RAiO
TECHNOLOGY INC.
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