240pin DDR2 SDRAM Unbuffered DIMMs based on 512 Mb 1st ver.
This Hynix unbuffered Dual In-Line Memory Module(DIMM) series consists of 512Mb 1st ver. DDR2 SDRAMs in Fine
Ball Grid Array(FBGA) packages on a 240pin glass-epoxy substrate. This Hynix 512Mb 1st ver. based DDR2 Unbuffered
DIMM series provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is
suitable for easy interchange and addition.
FEATURES
•
JEDEC standard Double Data Rate2 Synchrnous
DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power
Supply
All inputs and outputs are compatible with SSTL_1.8
interface
4 Bank architecture
Posted CAS
Programmable CAS Latency 3 , 4 , 5
OCD (Off-Chip Driver Impedance Adjustment)
ODT (On-Die Termination)
•
•
•
•
•
•
•
•
Fully differential clock operations (CK & CK)
Programmable Burst Length 4 / 8 with both sequen-
tial and interleave mode
Auto refresh and self refresh supported
8192 refresh cycles / 64ms
Serial presence detect with EEPROM
DDR2 SDRAM Package: 60ball FBGA(64Mx8), 84ball
FBGA(32Mx16)
133.35 x 30.00 mm form factor
Lead-free Products are RoHS compliant
•
•
•
•
•
•
ORDERING INFORMATION
Part Name
HYMP532U646-E3/C4
HYMP564U648-E3/C4
HYMP564U728-E3/C4
HYMP512U648-E3/C4
HYMP512U728-E3/C4
HYMP532U64P6-E3/C4
HYMP564U64P8-E3/C4
HYMP564U72P8-E3/C4
HYMP512U64P8-E3/C4
HYMP512U72P8-E3/C4
Density
256MB
512MB
512MB
1GB
1GB
256MB
512MB
512MB
1GB
1GB
Organization
32Mx64
64Mx64
64Mx72
128Mx64
128Mx72
32Mx64
64Mx64
64Mx72
128Mx64
128Mx72
# of
DRAMs
4
8
9
16
18
4
8
9
16
18
# of
ranks
1
1
1
2
2
1
1
1
2
2
Materials
Leaded
Leaded
Leaded
Leaded
Leaded
Lead free
Lead free
Lead free
Lead free
Lead free
ECC
None
None
ECC
None
ECC
None
None
ECC
None
ECC
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.0 / Apr. 2005
1
1240pin
DDR2 SDRAM Unbuffered DIMMs
SPEED GRADE & KEY PARAMETERS
E3 (DDR2-400)
Speed @CL3
Speed @CL4
Speed @CL5
CL-tRCD-tRP
400
400
-
3-3-3
C4 (DDR2-533)
400
533
-
4-4-4
Unit
Mbps
Mbps
Mbps
tCK
ADDRESS TABLE
Density Organization Ranks
256MB
512MB
512MB
1GB
1GB
32M x 64
64M x 64
64M x 72
128M x 64
128M x 72
1
1
1
2
2
SDRAMs
32Mb x 16
64Mb x 8
64Mb x 8
64Mb x 8
64Mb x 8
# of
DRAMs
4
8
9
16
18
# of row/bank/column Address
13(A0~A12)/2(BA0~BA1)/10(A0~A9)
13(A0~A12)/2(BA0~BA1)/10(A0~A9)
13(A0~A12)/2(BA0~BA1)/10(A0~A9)
14(A0~A13)/2(BA0~BA1)/10(A0~A9)
14(A0~A13)/2(BA0~BA1)/10(A0~A9)
Refresh
Method
8K / 64ms
8K / 64ms
8K / 64ms
8K / 64ms
8K / 64ms
Input/Output Functional Description
Symbol
CK[2:0], CK[2:0]
Type
SSTL
Polarity
Differential
Crossing
Pin Description
CK andk /CK are dirrerential clock inputs. All the DDR2 SDRAM addr/cntl inputs are sam-
pled on the crossing of positive edge of CK and negative edge of /CK. Output(read) data is
reference to the crossing of CK and /CK (Both directions of crossing)
Activates the DDR2 SDRAM CK signal when high and deactivates the CK signal when low.
CKE[1:0]
SSTL
Active High By deactivating the clocks, CKE low initiates the Power Down mode or the Self Refresh
mode.
Enables the associated DDR2 SDRAM command decoder when low and disables the com-
S[1:0]
SSTL
Active Low
mand decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue. Rank 0 is selected by S0; Rank 1 is selected by
S1
RAS, CAS, WE
ODT[1:0]
Vref
V
DDQ
BA[1:0]
SSTL
SSTL
Supply
Supply
SSTL
-
Active Low /RAS,/CAS and /WE(ALONG WITH S) define the command being entered.
Active High
Asserts on-die termination for DQ, DM, DQS and DQS signals if enabled via the DDR2
SDRAM mode register.
Reference voltage for SSTL18 inputs
Power supplies for the DDR2 SDRAM output buffers to provide improved noise immunity.
For all current DDR2 unbuffered DIMM designs, V
DDQ
shares the same power plane as V
DD
pins.
Selects which DDR2 SDRAM internal bank of four is activated.
Rev. 1.0 / Apr. 2005
2
1240pin
DDR2 SDRAM Unbuffered DIMMs
Symbol
Type
Polarity
Pin Description
During a Bank Activate command cycle, Address input difines the row address(RA0~RA15)
During a Read or Write command cycle, Address input defines the column address when
sampled at the cross point of the rising edge of CK and falling edge of CK. In addition to
A[9:0], A10/AP,
A[13:11]
SSTL
-
the column address, AP is used to invoke autoprecharge operation at the end of the burst
read or write cycle. If AP is high., autoprecharge is selected and BA0-BAn defines the bank
to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command
cycle., AP is used in conjunction with BA0-BAn to control which bank(s) to precharge. If AP
is high, all banks will be precharged regardless of the state of BA0-BAn inputs. If AP is low,
then BA0-BAn are used to define which bank to precharge.
DQ[63:0],
CB[7:0]
DM[8:0]
SSTL
-
Data and Check Bit Input/Output pins.
DM is an input mask signal for write data. Input data is masked when DM is sampled High
SSTL
Active High coincident with that input data during a write access. DM is sampled on both edges of
DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading.
Power and ground for the DDR2 SDRAM input buffers, and core logic.
V
DD
and V
DDQ
pins are tied to V
DD
/V
DDQ
planes on these modules.
Differential Data strobe for input and output data. For Rawcards using x16 organized DRAMs, DQ0~7
crossing
-
-
-
connect to the LDQS pin of the DRAMs and DQ8~15 connect to the UDQS pin of the DRAM
These signals are tied at the system planar to either V
SS
or V
DD
to configure the serial SPD
EEPROM.
This is a bidirectional pin used to transfer data into or out of the SPD EEPROM. A resister
must be connected to V
DD
to act as a pull up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be con-
nected from SCL to V
DD
to act as a pull up on the system board.
Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ power plane.
EEPROM supply is operable from 1.7V to 3.6V.
V
DD
,V
SS
DQS[8:0],
DQS[8:0]
SA[2:0]
SDA
SCL
VDDSPD
Supply
SSTL
Supply
PIN CONFIGURATION
Front Side
1 pin
64 pin
65 pin
120 pin
121 pin
184 pin
185 pin
240 pin
Back Side
Rev. 1.0 / Apr. 2005
3
1240pin
DDR2 SDRAM Unbuffered DIMMs
PIN ASSIGNMENT
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Name
VREF
VSS
DQ0
DQ1
VSS
DQS0
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1
DQS1
VSS
NC
NC
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DQS3
DQS3
VSS
DQ26
DQ27
Pin
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Name
VSS
NC(CB0)*
NC(CB1)*
VSS
NC(DQS8)*
NC(DQS8)*
VSS
NC(CB2)*
NC(CB3)*
VSS
VDDQ
CKE0
VDD
BA2
NC
VDDQ
A11
A7
VDD
A5
A4
VDDQ
A2
VDD
VSS
VSS
VDD
NC
VDD
A10/AP
BA0
VDDQ
WE
CAS
VDDQ
S1
ODT1
VDDQ
VSS
DQ32
Pin
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Name
DQ33
VSS
DQS4
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DQS5
DQS5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
SA2
NC,TEST
1
VSS
DQS6
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DQS7
DQS7
VSS
DQ58
DQ59
VSS
SDA
SCL
Pin
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
Name
VSS
DQ4
DQ5
VSS
DM0
NC
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
NC
VSS
CK1
CK1
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
NC
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DM3
NC
VSS
DQ30
DQ31
VSS
Pin
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
Name
NC(CB4)*
NC(CB5)*
VSS
NC(DM8)*
NC
VSS
NC(CB6)*
NC(CB7)*
VSS
VDDQ
CKE1
VDD
A15
A14
VDDQ
A12
A9
VDD
A8
A6
VDDQ
A3
A1
VDD
CK0
CK0
VDD
A0
VDD
BA1
VDDQ
RAS
S0
VDDQ
ODT0
A13
VDD
VSS
DQ36
DQ37
Pin
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Name
VSS
DM4
NC
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DM5
NC
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK2
CK2
VSS
DM6
NC
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DM7
NC
VSS
DQ62
DQ63
VSS
VDDSPD
SA0
SA1
* The pin names in parenthesises are applied to DIMM with ECC only.
*
NC=No connect
Notes :
1. The TEST pin is reserved for bus analysis tools and is not connected on standard memory module products(DIMMs).
2. NC Pins should not be connected to anything, including bussing within the NC group.
Rev. 1.0 / Apr. 2005
4
1240pin
DDR2 SDRAM Unbuffered DIMMs
FUNCTIONAL BLOCK DIAGRAM
256MB(32Mbx64) : HYMP532U64[P]6
/S 0
/ DQS 0
DQS 0
DM 0
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
/ LDQ S
LD Q S
LD M
I/ O 0
I/ O 1
I/ O 2
I/ O 3
I/ O 4
I/ O 5
I/ O 6
I/ O 7
/ CS
/ DQS 4
DQS 4
DM 4
D Q 32
D Q 33
D Q 34
D Q 35
D Q 36
D Q 37
D Q 38
D Q 39
/ DQS 5
DQS 5
DM 5
D Q 40
D Q 41
D Q 42
D Q 43
D Q 44
D Q 45
D Q 46
D Q 47
/ LDQ S
LD Q S
LDM
I/ O
I/ O
I/ O
I/ O
I/ O
I/ O
I/ O
I/ O
0
1
2
3
4
5
6
7
/ CS
D0
D2
/ DQS 1
DQS 1
DM 1
DQ 8
DQ 9
D Q 10
D Q 11
D Q 12
D Q 13
D Q 14
D Q 15
/ UDQS
UDQS
UDM
I/ O 8
I/ O 9
I/ O 1 0
I/ O 1 1
I/ O 1 2
I/ O 1 3
I/ O 1 4
I/ O 15
/ UDQS
UDQS
UDM
I/ O 8
I/ O 9
I/ O 1 0
I/ O 1 1
I/ O 1 2
I/ O 1 3
I/ O 1 4
I/ O 1 5
/ DQS 2
DQS 2
DM 2
D Q 16
D Q 17
D Q 18
D Q 19
D Q 20
D Q 21
D Q 22
D Q 23
/ LDQ S
LD Q S
LD M
I/ O
I/ O
I/ O
I/ O
I/ O
I/ O
I/ O
I/ O
0
1
2
3
4
5
6
7
/ CS
/ DQS 6
DQS 6
DM 6
D Q 48
D Q 49
D Q 50
D Q 51
D Q 52
D Q 53
D Q 54
D Q 55
/ DQS 7
DQS 7
DM 7
D Q 56
D Q 57
D Q 58
D Q 59
D Q 60
D Q 61
D Q 62
D Q 63
/ LDQ S
LD Q S
LDM
I/ O
I/ O
I/ O
I/ O
I/ O
I/ O
I/ O
I/ O
0
1
2
3
4
5
6
7
/ CS
D1
D3
/ DQS 3
DQS 3
DM 3
D Q 24
D Q 25
D Q 26
D Q 27
D Q 28
D Q 29
D Q 30
D Q 31
/ UDQS
UDQS
UDM
I/ O 8
I/ O 9
I/ O 1 0
I/ O 1 1
I/ O 1 2
I/ O 1 3
I/ O 1 4
I/ O 1 5
/ UDQS
UDQS
UDM
I/ O 8
I/ O 9
I/ O 1 0
I/ O 1 1
I/ O 1 2
I/ O 1 3
I/ O 1 4
I/ O 1 5
SCL
BA 0- BA 1
A 0 - A 13
/ RAS
/ CAS
CKE 0
/WE
ODT 0
VD D S P D
VD D / V D D Q
V REF
VS S
SCL
WP
A0
S A0
S e ria l P D
A1
S A1
SDA
SDRAMS
SDRAMS
SDRAMS
SDRAMS
SDRAMS
SDRAMS
SDRAMS
D 0 -D 3
D 0 -D 3
D 0 -D 3
D 0 -D 3
D 0 -D 3
D 0 -D 3
D 0 -D 3
A1
S A2
C lo c k S ig n a l L o a d s
C lo ck In p ut
C K 0 , /C K 0
SDRAM s
NC
C K 1 , /C K 1
S eria l P D
D O -D 3
2
C K 2 , /C K 2
2
D O -D 3
D O -D 3
N ote s :
1 . D Q ,D M ,D Q S ,/D Q S resisto rs : 2 2
Ω
+ /- 5 % .
2 . B a x,A x,/R A S ,/C A S ,/W E re sistors : 10
Ω
+ /- 5 % .
Rev. 1.0 / Apr. 2005
5
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