≤ 5.5 V. All minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted. All typical specifications are at T
A
= 25°C, V
DD1
= V
DD2
= 5 V.
Table 1.
Parameter
DC SPECIFICATIONS
Input Supply Current, per Channel, Quiescent
Output Supply Current, per Channel, Quiescent
ADuM2200, Total Supply Current, Two Channels
2
DC to 2 Mbps
V
DD1
Supply Current
V
DD2
Supply Current
10 Mbps (BR Grade Only)
V
DD1
Supply Current
V
DD2
Supply Current
ADuM2201, Total Supply Current, Two Channels
2
DC to 2 Mbps
V
DD1
Supply Current
V
DD2
Supply Current
10 Mbps (BR Grade Only)
V
DD1
Supply Current
V
DD2
Supply Current
For All Models
Input Currents
Logic High Input Threshold
Logic Low Input Threshold
Symbol
I
DDI (Q)
I
DDO (Q)
Min
Typ
0.4
0.5
Max
0.8
0.6
Unit
mA
mA
Test Conditions
I
DD1 (Q)
I
DD2 (Q)
I
DD1 (10)
I
DD2 (10)
1.3
1.0
3.5
1.7
1.7
1.6
4.6
2.8
mA
mA
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
5 MHz logic signal frequency
5 MHz logic signal frequency
I
DD1 (Q)
I
DD2 (Q)
I
DD1 (10)
I
DD2 (10)
I
IA
, I
IB
V
IH
V
IL
−10
0.7 (V
DD1
or V
DD2
)
1.1
1.3
2.6
3.1
+0.01
1.5
1.8
3.4
4.0
+10
mA
mA
mA
mA
μA
V
V
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
5 MHz logic signal frequency
5 MHz logic signal frequency
0 V ≤ V
IA
, V
IB
≤ V
DD1
or V
DD2
0.3
(V
DD1
or
V
DD2
)
(V
DD1
or
V
DD2
) − 0.1
(V
DD1
or
V
DD2
) − 0.5
5.0
4.8
0.0
0.04
0.2
0.1
0.1
0.4
Logic High Output Voltages
V
OAH
V
OBH
V
V
V
V
V
I
Ox
= −20 μA, V
Ix
= V
IxH
I
Ox
= −4 mA, V
Ix
= V
IxH
I
Ox
= 20 μA, V
Ix
= V
IxL
I
Ox
= 400 μA, V
Ix
= V
IxL
I
Ox
= 4 mA, V
Ix
= V
IxL
Logic Low Output Voltages
V
OAL
V
OBL
SWITCHING SPECIFICATIONS
ADuM220xAR
Minimum Pulse Width
3
Maximum Data Rate
4
Propagation Delay
5
Pulse Width Distortion, |t
PLH
− t
PHL
|
5
Propagation Delay Skew
6
Channel-to-Channel Matching
7
Output Rise/Fall Time (10% to 90%)
ADuM220xBR
Minimum Pulse Width
3
Maximum Data Rate
4
Propagation Delay
5
Pulse Width Distortion, |t
PLH
− t
PHL
|
5
Change vs. Temperature
PW
t
PHL
, t
PLH
PWD
t
PSK
t
PSKCD/OD
t
R
/t
F
PW
t
PHL
, t
PLH
PWD
10
20
5
Rev. 0 | Page 3 of 20
1000
1
20
150
40
100
50
10
100
50
3
ns
Mbps
ns
ns
ns
ns
ns
ns
Mbps
ns
ns
ps/°C
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
ADuM2200/ADuM2201
Parameter
Propagation Delay Skew
6
Channel-to-Channel Matching,
Codirectional Channels
7
Channel-to-Channel Matching,
Opposing Directional Channels
7
Output Rise/Fall Time (10% to 90%)
For All Models
Common-Mode Transient Immunity
at Logic High Output
8
Common-Mode Transient Immunity
at Logic Low Output
8
Refresh Rate
Input Dynamic Supply Current, per Channel
9
Output Dynamic Supply Current, per Channel
9
1
2
Symbol
t
PSK
t
PSKCD
t
PSKOD
t
R
/t
F
|CM
H
|
|CM
L
|
f
r
I
DDI (D)
I
DDO (D)
Min
Typ
Max
15
3
15
Unit
ns
ns
ns
ns
kV/μs
kV/μs
Mbps
mA/Mbps
mA/Mbps
Test Conditions
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
C
L
= 15 pF, CMOS signal levels
V
Ix
= V
DD1
or V
DD2
, V
CM
= 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
2.5
25
25
35
35
1.2
0.19
0.05
All voltages are relative to their respective ground.
The supply current values for both channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. See
Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through Figure 11
for total I
DD1
and I
DD2
supply currents as a function of data rate for ADuM2200 and ADuM2201 channel configurations.
3
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5
t
PHL
propagation delay is measured from the 50% level of the falling edge of the V
Ix
signal to the 50% level of the falling edge of the V
Ox
signal. t
PLH
propagation delay is
measured from the 50% level of the rising edge of the V
Ix
signal to the 50% level of the rising edge of the V
Ox
signal.
6
t
PSK
is the magnitude of the worst-case difference in t
PHL
and/or t
PLH
that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions.
7
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
8
CM
H
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V
DD2
. CM
L
is the maximum common-mode voltage slew rate
that can be sustained while maintaining V
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
9
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in the signal data rate. See Figure 6 through Figure 8 for
information on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating per-channel supply
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