Integrated
Circuit
Systems, Inc.
AV9170
AV9170-05 is only available through America II distributor
Clock Synchronizer and Multiplier
General Description
The
AV9170
generates an output clock which is
synchronized to a given continuous input clock with zero
delay (±1ns at 5V V
DD
). Using ICS’s proprietary phase-
locked loop (PLL) ana-log CMOS technology, the
AV9170
is useful for regenerating clocks in high speed systems
where skew is a major concern. By the use of the two
select pins, multiples or divisions of the input clock can
be generated with zero delay (see Tables 2 and 3). The
standard versions produce two outputs, where CLK2 is
always a divide by two version of CLK1.
The
AV9170
is also useful to recover poor duty cycle
clocks. A 50 MHz signal with a 20/80% duty cycle, for
example, can be regenerated to the 48/52% typical of the
part.
The
AV9170
allows the user to control the PLL feedback,
making it possible, with an additional 74F240 octal buffer
(or other such device that offers controlled skew outputs),
to synchronize up to 8 output clocks with zero delay
compared to the input (see Figure 1). Application notes for
the
AV9170
are available. Please consult ICS.
Features
•
•
•
•
•
•
•
•
•
•
•
On-chip Phase-Locked Loop for clocks
synchronization
Synchronizes frequencies up to 107 MHz
(output) @ 5.0V
±1ns skew (max) between input & output clocks @
5.0V
Can recover poor duty cycle clocks
CLK1 to CLK2 skew controlled to within ±1ns @
5.0V
3.0 - 5.5V supply range
Low power CMOS technology
Small 8-pin DIP or SOIC package
On chip loop filter
AV9170-01, -04
for output clocks 20-107 MHz @
5.0V, 20 - 66.7 MHz @ 3.3V
AV9170-02, -05
for output clocks 5-26.75 MHz @
5.0V, 5 - 16.7 MHz @ 3.3V
Block Diagram
0237G—07/18/05
AV9170
AV9170-05 is only available through America II distributor
Pin Configuration
8-Pin DIP or SOIC
Pin Descriptions
PIN
NUMBER
1
2
3
4
5
6
7
8
PIN NAME
FBIN
IN
GND
FS0
FS1
CLK1
VDD
CLK
TYPE
Input
Input
—
Input
Input
Output
—
Output
DESCRIPTION
FEEDBACK INPUT
INPUT for reference clock
GROUND
FREQUENCY SELECT 0
FREQUENCY SELECT 1
CLOCK output 1 (See Tables 1, 2, 3, 4, 5 for values)
Power Supply
CLOCK output 2 (See Tables 1, 2, 3, 4, 5 for values)
0237G—07/18/05
2
AV9170
AV9170-05 is only available through America II distributor
Using the AV9170
The
AV9170
has the following characteristics:
1. Rising edges at IN and FBIN are lined up. Falling
edges are not synchronized.
2. The relationship between the frequencies at FBIN
and IN with CLK1 feedback is shown in Table 1
below.
Eliminate High Speed
Clock Routing Problems
The
AV9170
makes it possible to route lower speed
clocks over long distances on the PC board and to place
an
AV9170
next to the device requiring a higher speed
clock. The multiplied output can then be used to produce
a phase locked, higher speed output clock.
Compensate for Propagation Delays
Including an
AV9170
in a timing loop allows the use of
PALs, gate arrays, etc., with loose timing specifications.
The
AV9170
compensates for the delay through the PAL
and synchronizes the output to the input reference clock.
Functionality (Table 1:)
FS1
0
0
1
1
FS0
0
1
0
1
fFBIN (-01, -02) fFBIN (-04, -05)
2 • fIN
4 • fIN
fIN
8 • fIN
3 • fIN
5 • fIN
6 • fIN
10 • f I N
Operating Frequency Range
The
AV9170
is offered in versions optimized for operation
in two frequency ranges. The -01 and -04 cover high
frequencies, 20 to 100 MHz.* The -02 and -05 operate
from 5 to 25 MHz.* The
AV9170
can be supplied with
custom multiplication factors and operating ranges.
Consult ICS for details.
3. The frequency of CLK2 is half the CLK1 frequency.
4. The CLK1 frequency ranges are:
V
DD
= 5V
AV9170-01, -04
AV9170-02, -05
20 < f
CLK1
<
5 < f
CLK1
<
107 MHz*
26.75 MHz*
V
DD
= 3.3V
< 66.7
< 16.7
3.3V VDD Operation
The
AV9170
does operate at both 5.0V and 3.3V system
conditions. Please note the Electrical Characteristic
specifica-tions at 3.3V include a limited output frequency
(66.6 MHz max.) and a wider skew of FBIN to CLK1. For
3.3V±5% (3.15V min.), this skew is -5.0 to 0 ns. At
3.3V±10% (3.0V min.), the skew is widened to -8 ns to
0 ns and should be accounted for in system design.
*At 3.3V, the maximum CLK1 frequency is 66.7 MHz for -
01, -04 and 16.7 MHz for -02, -05.
The
AV9170
will only operate correctly within these
frequency ranges.
Figure 1:
Application of
AV9170 for Multiple Outputs
0237G—07/18/05
3
AV9170
AV9170-05 is only available through America II distributor
Using CLK2 Feedback
Connecting CLK2 to FBIN as shown in Figure 2 will cause
all of the rising edges to be aligned (Figure 4).
Using CLK1 Feedback
With CLK1 connected to FBIN as shown in Figure 3, the
input and CLK1 output will be aligned on the rising edge,
but CLK2 can be either rising or falling (Figure 5). Consult
ICS if the CLK1 frequency is desired to be higher than 107
MHz.
Figure 2:
Figure 3:
For CLK2 frequencies 10 - 53.5 MHz* (-01)
For CLK2 frequencies 2.5 - 13.37 MHz (-02)
*Maximum 33.3MHz @ 3.3V (-01), 8.33MHz @ 3.3V (-02)
For CLK1 frequencies 20 - 107 MHz† (-01)
For CLK1 frequencies 5 - 26.75 MHz (-02)
†Maximum 66.7MHz @ 3.3V (-01), 16.7MHz @ 3.3V (-02)
Table 2:
Functionality Table for AV9170-01, -
02 with CLK2 Feedback
FS1
0
0
1
1
FS0
0
1
0
1
CLK1
INx4
INx8
INx2
INx16
CLK2
INx2
INx4
IN
INx8
Table 3:
Functionality Table for AV9170-01, -
02 with CLK1 Feedback
FS1
0
0
1
1
FS0
0
1
0
1
CLK1
INx2
INx4
IN
INx8
CLK2
IN
INx2
IN÷2
INx4
Figure 4:
Input and Output Clock Waveforms
with CLK2 Connected to FBIN
Figure 5:
Input and Output Clock Waveforms
with CLK1 Connected to FBIN
0237G—07/18/05
4
AV9170
AV9170-05 is only available through America II distributor
Using CLK2 Feedback
Connecting CLK2 to FBIN as shown in Figure 6 will cause
all of the rising edges to be aligned (Figure 8).
Using CLK1 Feedback
With CLK1 connected to FBIN as shown in Figure 7, the
input and CLK1 output will be aligned on the rising edge,
but CLK2 can be either rising or falling (Figure 9).
Figure 6:
Figure 7:
For CLK2 frequencies 10 - 53 MHz* (-04)
For CLK2 frequencies 2.5 - 13.37 MHz (-05)
*Maximum 33.3MHz @ 3.3V (-04), 8.33MHz @ 3.3V (-05)
For CLK1 frequencies 20 - 107 MHz† (-04)
For CLK1 frequencies 5 - 26.75 MHz (-05)
†Maximum 66.7MHz @ 3.3V (-04), 16.7MHz @ 3.3V (-05)
Table 4:
Functionality Table for AV9170-04, -
05 with CLK2 Feedback
FS1
0
0
1
1
FS0
0
1
0
1
CLK1
INx6
INx10
INx12
INx20
CLK2
INx3
INx5
INx6
INx10
Table 5:
Functionality Table for AV9170-04, -
05 with CLK1 Feedback
FS1
0
0
1
1
FS0
0
1
0
1
CLK1
INx3
INx5
INx6
INx10
CLK2
INx1.5
INx2.5
INx3
INx5
Figure 8:
Input and Output Clock Waveforms
with CLK2 Connected to FBIN
Figure 9:
Input and Output Clock Waveforms
with CLK1 Connected to FBIN
0237G—07/18/05
5
京公网安备 11010802033920号
EEWORLD
