XC6101~XC6107, XC6111~XC6117
Series
Voltage Detector (V
DF
=1.6V~5.0V)
ETR0207_014a
■GENERAL
DESCRIPTION
The XC6101~XC6107, XC6111~XC6117 series are groups of high-precision, low current consumption voltage detectors with
manual reset input and watchdog functions incorporating CMOS process technology. The series consist of a reference
voltage source, delay circuit, comparator, and output driver. With the built-in delay circuit, the XC6101 ~ XC6107, XC6111 ~
XC6117 series do not require any external components to output signals with release delay time. Moreover, with the manual
reset function, reset can be asserted at any time. The ICs produce two types of output; V
DFL
(low when detected) and V
DFH
(high when detected). With the XC6101 ~ XC6105, XC6111 ~ XC6115 series, the WD pin can be left open if the watchdog
function is not used. Whenever the watchdog pin is opened, the internal counter clears before the watchdog timeout occurs.
Since the manual reset pin is internally pulled up to the V
IN
pin voltage level, the ICs can be used by leaving the manual reset
pin unconnected if the pin is unused. The detect voltages are internally fixed 1.6V ~ 5.0V in increments of 0.1V, using laser
trimming technology. Six watchdog timeout periods are available in a range from 6.25ms to 1.6s. Seven release delay times
are available in a range from 3.13ms to 1.6s.
■APPLICATIONS
●Microprocessor
reset circuits
●Memory
battery backup circuits
●System
power-on reset circuits
●Power
failure detection
■FEATURES
: 1.6V ~ 5.0V, +2%
(0.1V increments)
Hysteresis Width
: V
DF
x 5%, TYP.
(XC6101~XC6107)
V
DF
x 0.1%, TYP.
(XC6111~XC6117)
Operating Voltage Range
: 1.0V ~ 6.0V
Detect Voltage Temperature
: +100ppm/
O
C (TYP.)
Coefficient
Output Configuration
: N-channel open drain,
CMOS
Reset Output Options
: V
DFL
(Low when detected)
V
DFH
(High when detected)
Watchdog Function
: Watchdog input WD;
If it remains ether high or low for
the duration of the watchdog
timeout period, a reset is
asserted.
Manual Reset Function
: Manual Reset Input MRB;
When it changes from high to
low, a reset is asserted.
Release Delay Time
: 1.6s, 400ms, 200ms, 100ms,
50ms, 25ms, 3.13ms (TYP.)
Watchdog Timeout Period
: 1.6s, 400ms, 200ms, 100ms,
50ms, 6.25ms (TYP.)
Detect Voltage Range
Packages
Environmentally Friendly
: SOT-25, USP-6C
:EU RoHS Compliant, Pb Free
■TYPICAL
APPLICATION CIRCUIT
V IN
μP
V IN
XC6101/XC6102
■TYPICAL
PERFORMANCE
CHARACTERISTICS
●Supply
Current vs. Input Voltage
XC61X1~XC61X5 (2.7V)
30
Supply Current:
ISS (μA)
25
20
15
10
5
0
Ta=-40
℃
Ta=25
℃
Ta=85
℃
Rpull
＊
RESETB
INPUT
I/O
VS S
V IN
RESETB
MRB
V SS
WD
* Not necessary with CMOS output products.
0
1
2
3
4
5
Input Voltage:
VIN (V)
6
* ‘x’ represents both ‘0’ and ‘1’. (ex. XC61x1⇒XC6101 and XC6111)
1/27
XC6101~XC6107, XC6111~XC6117 Series
■PIN
CONFIGURATION
●SOT-25
XC6101, XC6102 Series
XC6111, XC6112 Series
V
IN
5
WD
4
XC6103 & XC6113 Series
V
IN
5
WD
4
XC6104, XC6105 Series
XC6114, XC6115 Series
V
IN
5
WD
4
XC6106, XC6107 Series
XC6116, XC6117 Series
V
IN
5
MRB
4
1
RESETB
2
V
SS
3
MRB
1
RESET
2
V
SS
3
MRB
1
RESETB
2
3
1
RESETB
2
3
V
SS
RESET
V
SS
RESET
SOT-25 (TOP VIEW)
SOT-25 (TOP VIEW)
SOT-25 (TOP VIEW)
SOT-25 (TOP VIEW)
●USP-6C
XC6101, XC6102 Series
XC6111, XC6112 Series
V
IN
6
V
SS
5
RESETB
4
1
WD
2
MRB
3
NC
XC6103 & XC6113 Series
XC6104, XC6105 Series
XC6114, XC6115 Series
V
IN
6
V
SS
5
RESETB
4
1
WD
2
RESET
3
NC
XC6106, XC6107 Series
XC6116, XC6117 Series
V
IN
6
V
SS
5
RESETB
4
1
MRB
2
RESET
3
NC
V
IN
6
V
SS
5
RESET
4
1
WD
2
MRB
3
NC
USP-6C (BOTTOM VIEW)
USP-6C (BOTTOM VIEW)
USP-6C (BOTTOM VIEW)
USP-6C (BOTTOM VIEW)
* The dissipation pad for the USP-6C package should be
solder-plated in recommended mount pattern and metal
masking so as to enhance mounting strength and heat
release. If the pad needs to be connected to other pins, it
should be connected to the V
SS
(No.5) pin.
■PIN
ASSIGNMENT
PIN NUMBER
XC6101, XC6102
XC6103
XC6104, XC6105 XC6106, XC6107
PIN NAME
XC6111, XC6112
XC6113
XC6114, XC6115 XC6116, XC6117
SOT-25 USP-6C SOT-25 USP-6C SOT-25 USP-6C SOT-25 USP-6C
1
2
3
4
5
-
4
5
2
1
6
-
-
2
3
4
5
1
-
5
2
1
6
4
1
2
-
4
5
3
4
5
-
1
6
2
1
2
4
-
5
3
4
5
1
-
6
2
R
ESETB
V
SS
M
RB
WD
V
IN
RESET
FUNCTION
Reset Output
(V
DFL
: Low Level When Detected)
Ground
Manual Reset
Watchdog
Power Input
Reset Output
(V
DFH:
High Level When Detected)
2/27
XC6101 ~ XC6107, XC6111~ XC6117
Series
■PRODUCT
CLASSIFICATION
●Selection
Guide
MANUAL
RESET
Available
Available
Available
Not Available
Not Available
Available
Available
CMOS
N-channel open drain
-
CMOS
N-channel open drain
CMOS
N-channel open drain
RESET OUTPUT
V
DFL
(RESETB)
V
DFH
(RESET)
-
-
CMOS
CMOS
CMOS
CMOS
CMOS
SERIES
XC6101
XC6102
XC6103
XC6104
XC6105
XC6106
XC6107
XC6111
XC6112
XC6113
XC6114
XC6115
XC6116
XC6117
WATCHDOG
Available
Available
Available
Available
Available
Not Available
Not Available
●Ordering
Information
XC61①②③④⑤⑥⑦⑧-⑨
(
*1
)
DESIGNATOR
①
DESCRIPTION
Hysteresis Width
Functions and
Type of Reset Output
SYMBOL
0
1
1~7
A
B
C
③
Release Delay Time *
D
E
F
H
0
1
④
Watchdog Timeout Period
2
3
4
5
6
⑤⑥
Detect Voltage
16 ~ 50
MR
⑦⑧-⑨
Packages
Taping Type
(*2)
DESCRIPTION
V
DF
x 5% (TYP.) with hysteresis
V
DF
x 0.1% (TYP.) without hysteresis
Watchdog and manual functions, and reset
output type as per Selection Guide in the above
chart
3.13ms (TYP.)
25ms (TYP.)
50ms (TYP.)
100ms (TYP.)
200ms (TYP.)
400ms (TYP.)
1.6s (TYP.)
No WD timeout period for
XC6106, XC6107, XC6116, XC6117 Series
6.25ms (TYP.)
50ms (TYP.)
100ms (TYP.)
200ms (TYP.)
400ms (TYP.)
1.6s (TYP.)
Detect voltage
ex.) 4.5V:
⑤⇒4, ⑥⇒5
SOT-25
SOT-25
USP-6C
USP-6C
②
MR-G
ER
ER-G
* Please set the release delay time shorter than or equal to the watchdog timeout period.
ex.) XC6101D427MR or XC6101D327MR
(*1)
(*2)
The “-G” suffix indicates that the products are Halogen and Antimony free as well as being fully RoHS compliant.
The device orientation is fixed in its embossed tape pocket. For reverse orientation, please contact your local Torex sales office or
representative. (Standard orientation:
⑦R-⑨,
Reverse orientation:
⑦L-⑨)
3/27
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
