IS61WV25616EDBLL
IS64WV25616EDBLL
256K x 16 HIGH SPEED ASYNCHRONOUS
CMOS STATIC RAM WITH ECC
FEATURES
• High-speed access time: 8, 10 ns
• Low Active Power: 85 mW (typical)
• Low Standby Power: 7 mW (typical)
CMOS standby
• Single power supply
— V
dd
2.4V to 3.6V (10 ns)
— V
dd
3.3V ± 10% (8 ns)
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial and Automotive temperature support
• Lead-free available
• Error Detection and Error Correction
OCTOBER 2011
4,194,304-bit static RAMs organized as 262,144 words
by 16 bits. It is fabricated using
ISSI
's high-performance
CMOS technology. This highly reliable process coupled
with innovative circuit design techniques, yields high-
performance and low power consumption devices.
When
CE
is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be re-
duced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS61/64WV25616EDBLL is packaged in the JEDEC
standard 44-pin TSOP-II and 48-pin Mini BGA (6mm x
8mm).
DESCRIPTION
The
ISSI
IS61/64WV25616EDBLL is a high-speed,
FUNCTIONAL BLOCK DIAGRAM
Memory
Lower IO
Array-
256Kx8
8
4
Memory
Upper IO
A0-A17
Decoder
ECC
Array-
256K
x4
Array-
256Kx8
ECC
Array-
256K
x4
IO0-7
IO8-15
8
8
I/O Data
Circuit
8
8
ECC
ECC
12
12
8
Column I/O
4
/CE
/OE
/WE
/UB
/LB
Control
Circuit
Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-
est version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
09/29/2011
1
IS61/64WV25616EDBLL
PIN CONFIGURATIONS
44-Pin LQFP*
48-Pin mini BGA (6mm x 8mm)
1
2
3
4
5
6
1
2
3
CE
I/O0
I/O1
I/O2
I/O3
VDD
GND
I/O4
I/O5
I/O6
I/O7
44 43 42 41 40 39 38 37 36 35 34
33
1
32
2
31
3
30
4
29
5
TOP VIEW
28
6
27
7
26
8
25
9
24
10
23
11
12 13 14 15 16 17 18 19 20 21 22
WE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A17
A16
A15
A14
A13
A12
A11
A10
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
VDD
I/O11
I/O10
I/O9
I/O8
NC
A
B
C
D
E
F
G
H
LB
I/O
8
I/O
9
GND
V
DD
I/O
14
I/O
15
NC
OE
UB
I/O
10
I/O
11
I/O
12
I/O
13
NC
A8
A0
A3
A5
A17
NC
A14
A12
A9
A1
A4
A6
A7
A16
A15
A13
A10
A2
CE
I/O
1
I/O
3
I/O
4
I/O
5
WE
A11
N/C
I/O
0
I/O
2
V
DD
GND
I/O
6
I/O
7
NC
4
5
6
7
8
9
10
11
12
*LQFP package under evaluation.
PIN DESCRIPTIONS
A0-A17
I/O0-I/O15
CE
OE
WE
LB
UB
NC
V
dd
GND
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
Lower-byte Control (I/O0-I/O7)
Upper-byte Control (I/O8-I/O15)
No Connection
Power
Ground
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
09/29/2011
3
IS61/64WV25616EDBLL
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
term
V
dd
t
stg
P
t
Parameter
Terminal Voltage with Respect to GND
V
dd
Relates to GND
Storage Temperature
Power Dissipation
Value
–0.5 to V
dd
+ 0.5
–0.3 to 4.0
–65 to +150
1.0
Unit
V
V
°C
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
CAPACITANCE
(1,2)
Symbol
c
In
c
I/o
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
V
In
= 0V
V
out
= 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
a
= 25°c,
f = 1 MHz, V
dd
= 3.3V.
ERROR DETECTION AND ERROR CORRECTION
•
•
•
•
Independent ECC for each byte
Detect and correct one bit error per byte
Better reliability than parity code schemes which can only detect an error but not correct an error
Backward Compatible: Drop in replacement to current in industry standard devices (without ECC)
OPERATING RANGE (V
DD
)
1
Range
Industrial
Automotive (A1)
Automotive (A3)
Ambient Temperature
–40°C to +85°C
–40°C to +85°C
–40°C to +125°C
IS61WV25616EDBLL
V
DD
(8, 10n
S
)
2.4V-3.6V (10ns)
3.3V ± 10% (8ns)
—
—
IS64WV25616EDBLL
V
DD
(10n
S
)
—
2.4V-3.6V
2.4V-3.6V
Note:
1. Contact SRAM@issi.com for 1.8V option
4
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
09/29/2011
IS61/64WV25616EDBLL
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
V
DD
= 3.3V + 10%
Symbol
V
oH
V
oL
V
IH
V
IL
I
LI
I
Lo
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
(1)
Input Leakage
Output Leakage
Test Conditions
V
dd
=
Min., I
oH
=
–4.0 mA
V
dd
=
Min., I
oL
=
8.0 mA
GND ≤ V
In
≤
V
dd
GND ≤ V
out
≤
V
dd
,
Outputs Disabled
Min.
2.4
—
2
–0.3
–1
–1
Max.
—
0.4
V
dd
+ 0.3
0.8
1
1
Unit
V
V
V
V
µA
µA
1
2
3
4
Note:
1. V
IL
(min.) = –0.3V DC; V
IL
(min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
V
IH
(max.) = V
dd
+ 0.3V
dc; V
IH
(max.) = V
dd
+ 2.0V
ac (pulse width < 10 ns). Not 100% tested.
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
V
DD
= 2.4V-3.6V
Symbol
V
oH
V
oL
V
IH
V
IL
I
LI
I
Lo
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
(1)
Input Leakage
Output Leakage
Test Conditions
V
dd
=
Min., I
oH
=
–1.0 mA
V
dd
=
Min., I
oL
=
1.0 mA
GND ≤
V
In
≤
V
dd
GND ≤
V
out
≤
V
dd
,
Outputs Disabled
Min.
1.8
—
2.0
–0.3
–1
–1
Max.
—
0.4
V
dd
+ 0.3
0.8
1
1
Unit
V
V
V
V
µA
µA
5
6
7
8
Note:
1.
V
IL
(min.) = –0.3V DC; V
IL
(min.) = –2.0V AC (pulse width < 10 ns). Not 100% tested.
V
IH
(max.) = V
dd
+ 0.3V
dc; V
IH
(max.) = V
dd
+ 2.0V
ac (pulse width < 10 ns). Not 100% tested.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
Symbol
I
cc
I
cc
1
I
sb
1
Parameter
V
dd
Dynamic Operating
Supply Current
Operating
Supply Current
TTL Standby Current
(TTL Inputs)
CMOS Standby
Current (CMOS Inputs)
Test Conditions
V
dd
=
Max.,
I
out
= 0
mA, f = f
maX
V
dd
=
Max.,
I
out
= 0
mA, f = 0
V
dd
=
Max.,
V
In
= V
IH
or V
IL
CE ≥ V
IH
, f = 0
V
dd
=
Max.,
CE ≥ V
dd
– 0.2V,
V
In
≥
V
dd
– 0.2V,
or
V
In
≤
0.2V,
f = 0
-8
Min. Max.
— 40
— 45
— —
21
— 20
— 25
— —
—
10
— 15
— —
—
5
—
6
— —
1.5
-10
Min. Max.
— 30
— 35
— 50
21
—
—
—
—
—
—
—
—
—
1.5
20
25
40
10
15
30
5
6
15
-20
Min. Max.
— 25
— 30
— 45
—
—
—
—
—
—
—
—
—
20
25
40
10
15
30
5
6
15
Unit
mA
mA
mA
Com.
Ind.
Auto.
typ.
(2)
Com.
Ind.
Auto.
Com.
Ind.
Auto.
Com.
Ind.
Auto.
typ.
(2)
9
10
11
12
I
sb
2
mA
Note:
1. At f = f
maX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
2. Typical values are measured at V
dd
= 3.0V, T
a
= 25
o
C and not 100% tested.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. A
09/29/2011
5
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
